![](https://csdnimg.cn/release/download_crawler_static/88673369/bg4.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
APU_SVC
APU_PROCHOT#
APU_THERMTRIP#
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
DP_ZVSS
LTDP0_HPD
APU_SIC
APU_SID
APU_SVD
APU_ALERT#_R
APU_SIC
APU_SID
TEST19
TEST18
DAC_ZVSS
TEST25_H
TEST_25_L
HDMI_TX2N_C
HDMI_TX2P_C
HDMI_TX0N_C
HDMI_TX0P_C
HDMI_TX1N_C
HDMI_TX1P_C
HDMI_CLKN_C
HDMI_CLKP_C
APU_PROCHOT#
FCH_SID
FCH_SIC
EC_SMB_DA2
EC_SMB_CK2
EC_SMB_CKAPU_SIC
EC_SMB_DAAPU_SID
APU_THERMTRIP#
TEST31
TEST36
TEST37
TEST15
TEST_25_L
TEST33_H
TEST33_L
TEST36
EDID_CLK
EDID_DATA
APU_ALERT#_R
HDMI_DATA
HDMI_CLK
HDMI_DATA
HDMI_CLK
APU_PROCHOT#
APU_TDO
APU_PWRGD
LDT_RST#
APU_TCK
APU_DBRDY
APU_TMS
APU_DBREQ#
APU_TDI
TEST35
APU_TRST#
LDT_RST#
APU_PWRGD
APU_PROCHOT#
APU_SVC
APU_SVD
APU_SIC
APU_SID
ALLOW_STOP#
DMIC_CLK
+1.8VS
+3VS
+3VS
+1.8VS
+3VS
+1.8VS
+3VS
+1.8VS
HDMI_TX2P<10>
HDMI_TX2N<10>
HDMI_TX1P<10>
HDMI_TX1N<10>
HDMI_TX0P<10>
HDMI_TX0N<10>
HDMI_CLKP<10>
HDMI_CLKN<10>
LVDS_A1<9>
LVDS_A1#<9>
LVDS_A0<9>
LVDS_A0#<9>
LVDS_ACLK<9>
LVDS_ACLK#<9>
LVDS_A2<9>
LVDS_A2#<9>
APU_CLK<12>
APU_CLK#<12>
DISP_CLK<12>
DISP_CLK#<12>
APU_SVC<36>
APU_SVD<36>
APU_PWRGD<12>
LDT_RST#<12>
APU_ALERT#_FCH<14>
APU_ALERT#_EC<26>
APU_VDDNB_RUN_FB_H<36>
APU_VDD0_RUN_FB_H<36>
APU_VDD0_RUN_FB_L<36>
FCH_PROCHOT#<12>
EC_PROCHOT#<26>
H_THERMTRIP# <13>
FCH_SID <13>
EC_SMB_DA2 <26>
FCH_SIC <13>
EC_SMB_CK2 <26>
APU_ENBKL <26>
APU_ENVDD <9>
APU_BLPWM <9>
HDMI_CLK <10>
DAC_RED <11>
DAC_GRN <11>
DAC_BLU <11>
CRT_HSYNC <11>
CRT_VSYNC <11>
CRT_DDC_CLK <11>
CRT_DDC_DATA <11>
HDMI_DET <10>
HDMI_DATA <10>
EDID_CLK <9>
EDID_DATA <9>
ALLOW_STOP# <12>APU_VDDNB_RUN_FB_L<36>
DMIC_CLK <9,17>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
P1VE6 Schematics
1.0
FT1 CTRL/DP/CRT
Custom
4 37Thursday, March 17, 2011
2010/11/09 2012/11/09
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
P1VE6 Schematics
1.0
FT1 CTRL/DP/CRT
Custom
4 37Thursday, March 17, 2011
2010/11/09 2012/11/09
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
P1VE6 Schematics
1.0
FT1 CTRL/DP/CRT
Custom
4 37Thursday, March 17, 2011
2010/11/09 2012/11/09
Compal Electronics, Inc.
T0 FCH
TO EC
TO EC
T0 FCH
Vgs(th): min 1.0V
Typ 1.6V
Max 2.0V
2N7002DW-T/R7
If FCH internal pull-up disabled, level-shifter could be deleted.
Need BIOS to disable internal pull-up!!
Close to APU
Connection to EC, FCH input need to pull-down
AMD Debug
If Q8 or R429, R432 implemented,
EC side pull-up need to be mounted
8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)
Power Circuit
Power Circuit
Power Circuit
8/25 Pull-up 100k(@ R352) to +3VS
on LTDP0_HPD for eDP
8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P
R9 R352
Display
mount
@
@
LVDS
eDP
*
mount
9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L
9/9 Change R24 from @ to mount R26 from mount to @
9/9 Add R386 (1k@) to +1.8VS on TEST35
9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)
9/15 Change R24 from mount to @
9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32
9/20 Delete R41~R43
10/01 Remove T1,T3~T7,T11,T12,T31,T32
10/05 Add 100p(C405) on LDT_RST#
SA00004KD50
Reserve C421 for APU_PWRGD
Michael 2010/11/18
Add C429 for APU_PROCHOT#
Michael 2010/11/18
Reserve C432, C433, C434, C435
Michael 2010/11/18
Reserve C438 for ALLOW_STOP#
Michael 2010/11/18
Change R10, R11 to RP1
Michael 2010/12/23
Reserve R389 for eDP function
Tock 2010/12/30
APU C50 P/N change to SA00004KD50
Tock 2010/12/30
C8 .1U_0402_16V7KC8 .1U_0402_16V7K
1 2
R47 0_0402_5%
@
R47 0_0402_5%
@
1 2
E
B
C
Q1
MMBT3904_NL_SOT23-3
E
B
C
Q1
MMBT3904_NL_SOT23-3
2
3 1
T8
PAD
T8
PAD
R35 1K_0402_5%R35 1K_0402_5%
12
R36 1K_0402_5%R36 1K_0402_5%
12
C421
100P_0402_50V8J
@
C421
100P_0402_50V8J
@
1
2
R49 0_0402_5%R49 0_0402_5%
1 2
R18 150_0402_1%R18 150_0402_1%
1 2
R1 150_0402_1%R1 150_0402_1%
1 2
R9 100K_0402_5%R9 100K_0402_5%
1 2
R24 0_0402_5%@R24 0_0402_5%@
1 2
R14 1K_0402_5%R14 1K_0402_5%
1 2
R352 100K_0402_5%@R352 100K_0402_5%@
1 2
C438
100P_0402_50V8J
@
C438
100P_0402_50V8J
@
1
2
C2 .1U_0402_16V7KC2 .1U_0402_16V7K
1 2
R51 0_0402_5%R51 0_0402_5%
1 2
R19 499_0402_1%R19 499_0402_1%
1 2
R379 0_0402_5%R379 0_0402_5%
1 2
R22 1K_0402_5%R22 1K_0402_5%
1 2
C3 .1U_0402_16V7KC3 .1U_0402_16V7K
1 2
R4 1K_0402_5%R4 1K_0402_5%
1 2
R48 0_0402_5%R48 0_0402_5%
1 2
R33
1K_0402_5%
R33
1K_0402_5%
1 2
R5 300_0402_5%R5 300_0402_5%
12
R386 1K_0402_5%R386 1K_0402_5%
1 2
R10 10K_0402_5%R10 10K_0402_5%
1 2
R20 1K_0402_5%R20 1K_0402_5%
1 2
R26 0_0402_5%@R26 0_0402_5%@
1 2
R3 1K_0402_5%R3 1K_0402_5%
1 2
R29 51_0402_1%R29 51_0402_1%
1 2
R6 1K_0402_5%R6 1K_0402_5%
1 2
T29
PAD
T29
PAD
R30 1K_0402_5%@R30 1K_0402_5%@
1 2
R380 0_0402_5%R380 0_0402_5%
1 2
T13
PAD
T13
PAD
G
D
S
Q2A
DMN66D0LDW-7_SOT363-6
@
G
D
S
Q2A
DMN66D0LDW-7_SOT363-6
@
2
61
R21 1K_0402_5%R21 1K_0402_5%
1 2
C7 .1U_0402_16V7KC7 .1U_0402_16V7K
1 2
C1 .1U_0402_16V7KC1 .1U_0402_16V7K
1 2
C429
100P_0402_50V8J
@
C429
100P_0402_50V8J
@
1
2
TEST
VGA DAC
JTAG CTRL
SER
CLK
DP MISC
DISPLAYPORT 0
DISPLAYPORT 1
U1B
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
TEST
VGA DAC
JTAG CTRL
SER
CLK
DP MISC
DISPLAYPORT 0
DISPLAYPORT 1
U1B
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
RSVD_3
V5
RSVD_2
W11
RSVD_1
B4
VSS_SENSE
F1
VDDIO_MEM_S_SENSE
F3
VDDCR_CPU_SENSE
G1
VDDCR_NB_SENSE
F4
DBREQ_L
M1
DBRDY
M3
TRST_L
M4
TCK
P1
TDO
N1
TDI
N2
ALERT_L
T2
THERMTRIP_L
U2
PROCHOT_L
U1
PWROK
T4
RESET_L
T3
SID
P4
SIC
P3
SVD
J2
SVC
J1
DISP_CLKIN_L
D1
DISP_CLKIN_H
D2
CLKIN_L
V1
CLKIN_H
V2
LTDP0_TXN3
C8
LTDP0_TXP3
D8
LTDP0_TXN2
B6
LTDP0_TXP2
A6
LTDP0_TXN1
C6
LTDP0_TXP1
D6
LTDP0_TXN0
A5
LTDP0_TXP0
B5
TDP1_TXP3
A10
TDP1_TXN2
C10
TDP1_TXN1
A9
TDP1_TXP1
B9
TDP1_TXN0
B8
TDP1_TXP0
A8
DMAACTIVE_L
T1
TEST38
K3
TEST37
R5
TEST36
N5
TEST35
H4
TEST34_L
T15
TEST34_H
U15
TEST33_L
J19
TEST33_H
J18
TEST31
M21
TEST28_L
M5
TEST28_H
L5
TEST25_L
K2
TEST25_H
K1
TEST19
M2
TEST18
L2
TEST17
L1
TEST16
K4
TEST15
E4
TEST14
T5
TEST6
R6
TEST5
R2
TEST4
R1
DAC_ZVSS
D12
DAC_SDA
D4
DAC_SCL
F2
DAC_VSYNC
E2
DAC_HSYNC
E1
DAC_BLUEB
B13
DAC_BLUE
A13
DAC_GREENB
B12
DAC_GREEN
A12
DAC_REDB
D13
DAC_RED
C12
LTDP0_HPD
D3
LTDP0_AUXN
B3
LTDP0_AUXP
A3
TDP1_HPD
C1
TDP1_AUXN
C2
TDP1_AUXP
B2
DP_VARY_BL
H1
DP_DIGON
H2
DP_BLON
G2
DP_ZVSS
H3
TDP1_TXP2
D10
TDP1_TXN3
B10
TMS
P2
R23 0_0402_5%@R23 0_0402_5%@
1 2
R16 1K_0402_5%R16 1K_0402_5%
1 2
C434
100P_0402_50V8J
@
C434
100P_0402_50V8J
@
1
2
R32
10K_0402_5%
<BOM Structure>
R32
10K_0402_5%
<BOM Structure>
12
R8 510_0402_1%R8 510_0402_1%
1 2
G
D
S
Q2B
DMN66D0LDW-7_SOT363-6
@
G
D
S
Q2B
DMN66D0LDW-7_SOT363-6
@
5
34
R11 10K_0402_5%R11 10K_0402_5%
1 2
R389 0_0402_5%
eDP@
R389 0_0402_5%
eDP@
1 2
C432
100P_0402_50V8J
@
C432
100P_0402_50V8J
@
1
2
R52 0_0402_5%R52 0_0402_5%
1 2
R38 1K_0402_5%R38 1K_0402_5%
12
R13 1K_0402_5%R13 1K_0402_5%
1 2
R27 0_0402_5%R27 0_0402_5%
1 2
R12 150_0402_1%R12 150_0402_1%
1 2
C4 .1U_0402_16V7KC4 .1U_0402_16V7K
1 2
R15 150_0402_1%R15 150_0402_1%
1 2
R28 51_0402_1%R28 51_0402_1%
1 2
R17 1K_0402_5%R17 1K_0402_5%
1 2
C435
100P_0402_50V8J
@
C435
100P_0402_50V8J
@
1
2
C433
100P_0402_50V8J
@
C433
100P_0402_50V8J
@
1
2
C9 0.1U_0402_16V4ZC9 0.1U_0402_16V4Z
1 2
R31 1K_0402_5%R31 1K_0402_5%
1 2
C405 100P_0402_50V8JC405 100P_0402_50V8J
1 2
C6 .1U_0402_16V7KC6 .1U_0402_16V7K
1 2
R2 300_0402_5%R2 300_0402_5%
12
C10 0.1U_0402_16V4ZC10 0.1U_0402_16V4Z
1 2
R34 0_0402_5%@R34 0_0402_5%@
1 2
R50 0_0402_5%
@
R50 0_0402_5%
@
1 2
R7 300_0402_5%R7 300_0402_5%
12
R39
10K_0402_5%
@
R39
10K_0402_5%
@
12
T14PADT14PAD
T30
PAD
T30
PAD
C5 .1U_0402_16V7KC5 .1U_0402_16V7K
1 2
R25 510_0402_1%R25 510_0402_1%
1 2
R37 1K_0402_5%R37 1K_0402_5%
12