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Lenovo_Z360_-_QUANTA_LL7A_DISCRETE_GFX_-_REV_1ASec.pdf
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A A
B B
C C
D D
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
1 42
Custom
BLOCK DIAGRAM
Monday, February 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
1 42
Custom
BLOCK DIAGRAM
Monday, February 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
1 42
Custom
BLOCK DIAGRAM
Monday, February 08, 2010
LL7A Intel Calpella Platform with Discrete GFX
Nvidia NV11N
PCIEx16
PCI-Express GFX
( rPGA 989 )
PCH
DMI X 4
SATA
IHDA
AUDIO
DC/DC
AC/BATT
CONNECTOR
BATT
CHARGER
Auburndale /
Arrandale
LVDS
RUN POWER SW
VGA
USB2.0 x 2
USB conn x 2
SPI
PS/2
KeyboardTouchpad
LPC
SATA-HDD
SATA
KBC
ITE8502
USB2.0
MINI-CARD (F1)
WWAN/SSD
USB2.0
PCIEX1
CPU CoreREGULATOR
3VPCU, 5VPCU, +15V
POWER
+1.05V_VTT,+1.05V_PCH
REGULATOR (DDR3)
1.5VSUS, SMDDR_VREF,1.5V
POWER
3VSUS, 5VSUS, 3V_S5, 5V_S5
SATA-ODD
RJ45/Magnetics
LAN
MINI-CARD
WLAN/WiMAX
Audio Jacks
Audio
SPK conn
AL272
Camera
FLASH
512Kbyts
USB2.0
PCIEx1
DDR3 x 4
(512M/1G)
FAN
FAN G993P11U
PG 4,5,6,7
PG 8,9,10,11,12,13
PG 16,17,18,19,20PG 21
PG 35
PG 35
PG 31
PG 30
PG 29
PG 28
PG 28
PG 36 PG 36
PG 26
PG 26
PG 26
PG 25 PG 25
PG 42
PG 44
PG 43
VGA Core
PG 47
PG 46
PG 45
PG 44PG 42
PG 22
DDR3 - SODIMM0
DDR3 - SODIMM1
Dual Channel DDR3
800/1067 1.5V
SLG8SP595V(QFN32)
14.318MHz
CLOCK GEN
PG 3
PG 37
PG 15
PG 14
Atheros 8151/8152
+1.8V
REGULATOR
PG 44
Headphone
Microphone
25MHz
32.768KHz
Discrete
+3V, +5V
01
PCIEx1
USB2.0
32.768KHz
Bluetooth
USB2.0
PG 34
SPI
Discharge
PG 40
Ibex Peak-M
Intel(R) 5 Series
Express Chipset
FDI
CRT CONN.
Panel Connector
PG 22
PG 23
Re-Driver
PG 29
USB2.0 x 1
SATA
USB+eSATA
PG 29
FLASH 4Mbyts
PG 9
OZ600FJ
5-in-1 Card Reader
Card Reader CONN.
PG 27
PG30
HDMI CONN.
HDMI
DMIC
hexainf@hotmail.com
1
1
2
2
3
3
4
4
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5
6
6
7
7
8
8
A A
B B
C C
D D
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
2 42
C
FRONTPAGE
Monday, February 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
2 42
C
FRONTPAGE
Monday, February 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
2 42
C
FRONTPAGE
Monday, February 08, 2010
PAGE DESCRIPTION
2
1
Ibex Peak-M
Table of Contents Power States
POWER PLANE
+5V_ODD
3
4-7
15-19
21
22
23
24
25
27
5VSUS
CONTROL
SIGNAL
3VSUS
+5V
+3V
+1.8V
+1.05V_VTT
+1.5V
+3VRTC
VCC_CORE
Front Page
28
29
33
34
0.75VSMDDR_VTERM
LCDVCC
37
CARD READER(OZ600FJ)
+1.05V_PCH
USB X2/SIM_CARD/LEDs/RF
USB x 2 /USB+ ESATA
ATHEROS (AR8151/AR8152)
35
Schematic Block Diagram
CLOCK GENERATOR
Arrandale CPU
8-12
13-14
DDRIII SO-DIMM
Discreate VGA (N11M-GE2)
HDMI Conn.
CRT Conn.
ONFI
Express Card
G-Sensor
MINI-Card ( WWAN/SSD)
38
B To B Conn.
39
40
41
42
3V/5V (MAX17101)
DDR3 (TPS5116REGR)
AL272/AMP/MIC/SPK
26
MINI-Card (WLAN)
36
1.05V_VTT & 1.05_PCH (RT8204)
LANVCC
DESCRIPTION
ACTIVE INVOLTAGE PAGE
VIN
3VPCU
5VPCU
+15V
1.5VSUS
+5V_HDD
BAT-V
10V~+20V
+3.0V~+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+5V
+5V
+5V
+5V
+5V
+15V
+1.5V
+1.8V
+0.75V
+1.5V
+1.05V
+1.05V
+3.3V
23,32,43,44,45,46,47,48,49,50
9,12,41
9,23,27,30,32,35,39,41,43,44,47
14,43,44,45,46,47,49,50
23,38,43,45,46,47
27,43
23,39,43,48
14,15,30,34,41,43,49
4,6,14,15,43,45,46,49,50
14,15,43,45
12,18,23,24,25,26,28,35,37,41,43,44
3,4,8,9,10,11,12,14,15,17,23,25,26,27,28,29,
30,31,32,33,34,36,37,38,39,40,41,43,44,45,46
,47,48,50,52
12,18,19,20,31,32,34,45,46
4,6,11,12,43,46,48,52
3,10,12,43,46,52
6,43,48
23
28
MAIN BATTERY+10V~+17V
MAIN POWER
RTC
ITE8052 POWER
LARGE POWER
SLP_S3# CTRLD POWER
SLP_S3# CTRLD POWER
LAN POWER
DC/DC POWER IC SOURCE
SODIMM POWER
Sys Management,PCH Resume
Well,Intel HD Audio,USB,WLAN
WiMAX POWER
DDR3 SODIMM REFERENCE POWER
LVDS,NVM POWER
Mini PCIe,Express Card POWER
CPU CORE POWER
AuBurndale VTT POWER
PCH CORE POWER
HDD Power
ODD Power
LCD Power
3V5V_EN
3V5V_EN
3V5V_EN
LAN_ON
SUSON
SUSON
SUSON
MAIN_ON
MAIN_ON
MAIN_ON
MAIN_ON
MAIN_ON
1.05V_RUN_ON
VRON
ENVDD
MAIN_ON
MAIN_ON
CHG_PBATT
S0~S5
S0~S5
S0~S5
S0~S5
S0~S520
LCD + Camera Conn.
K/B & T/P
BLUETOOTH
FAN & Thermal
47
45
46
iTPM & RFID EEPROM
KBC IT8502E
48
CPU (MAX17082)
28
6,12,17,18,21,22,33,43,50
Power Block Dianram
51
DIS_1.8V_RUN (OZ8116LN)
50
DIS_GFX_VCC (MAX8792)
49
Charger
44
43
Discharge
HOLD & SKEW
02
+VCC_GFX_CORE 18,21,43,49+0.9V~+1.2V VGA CORE POWER
MAIN_ON
53
54
Revision & Schematic Value Description
BOM Matrix Table
52
XDP
GFXVR_EN
3V_S5 +3.3V 8,9,10,11,12,43,52 S5_ON
5V_S5 +5V S5_ONPCH SUS POWER12,29,30,43
SLP_S4# CTRLD POWER
SLP_S4# CTRLD POWER
S0~S3
S0~S3
S0~S3
S0~S3
S0~S3
S0
S0
S0
S0
S0
S0
S0
S0
S0
S0
S0
S0
S0~S5
44
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
CK_PWRGD_R
XTAL_IN XTAL_OUT
XTAL_IN
XTAL_OUT
CPU_SELCLK_ICH_14M
CK_PWRGD_R
CPU_SEL
CLK_BUF_DREFCLK
CLK_BUF_DREFCLK#
CLK_BUF_PCIE_3GPLL
CLK_BUF_PCIE_3GPLL#
CLK_BUF_DREFSSCLK
CLK_BUF_DREFSSCLK#
CLK_BUF_BCLK_P
CLK_BUF_BCLK_N
CLK_VGA_27M_NOSS
CLK_VGA_27M_SS
VR_PWRGD_CLKEN#(40)
CLK_27M_SS (17)
CLK_ICH_14M(9)
CGCLK_SMB(9,13,14)
CGDAT_SMB(9,13,14)
CLK_BUF_DREFCLK (9)
CLK_BUF_DREFCLK# (9)
CLK_BUF_PCIE_3GPLL (9)
CLK_BUF_PCIE_3GPLL# (9)
CLK_BUF_DREFSSCLK (9)
CLK_BUF_DREFSSCLK# (9)
CLK_BUF_BCLK_P (9)
CLK_BUF_BCLK_N (9)
CLK_27M_NOSS (17)
+1.05V_VTT(4,6,8,9,10,11,12,35,38,40,42)
+1.5V(27,28,37)
+3V(4,8,9,10,11,12,13,14,15,20,21,22,24,25,26,27,28,29,30,31,32,33,35,36,40,41)
+3V
+3V
+VDDIO_CLK
+3V
+3V
+1.5V
+VDDCORE_CLK
+VDDIO_CLK
+VDDSE_CLK
+VDDCORE_CLK
+VDDSE_CLK+3V
+3V
+1.05V_VTT
VIN
+1.05V_VTT
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
3 42
B
CLOCK GEN(9LVS3197)
Thursday, April 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
3 42
B
CLOCK GEN(9LVS3197)
Thursday, April 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
3 42
B
CLOCK GEN(9LVS3197)
Thursday, April 08, 2010
03
Place each 0.1uF cap close to pin
CPU_SEL
0
CPU0/1=133MHz
(default)
CPU0/1=100MHz
25mA 150mA
Place each 0.1uF cap close to pin Place each 0.1uF cap close to pin
150mA
Place R8044 within 0.5" of C/G
Discrete only
EMI request
C236
0.1U/25V/X5R_4
C236
0.1U/25V/X5R_4
L16
HCB1608KF-181T15_6
L16
HCB1608KF-181T15_6
1 2
C235 0.1U/10V/X5R_4C235 0.1U/10V/X5R_4
C387 0.1U/10V/X5R_4C387 0.1U/10V/X5R_4
L19
HCB1608KF-181T15_6
L19
HCB1608KF-181T15_6
1 2
C229 0.1U/10V/X5R_4C229 0.1U/10V/X5R_4
C230 0.1U/10V/X5R_4C230 0.1U/10V/X5R_4
C233
33P/50V/NPO_4
C233
33P/50V/NPO_4
12
C268 0.1U/10V/X5R_4C268 0.1U/10V/X5R_4
C377 0.1U/10V/X5R_4C377 0.1U/10V/X5R_4
C672 0.1U/10V/X5R_4C672 0.1U/10V/X5R_4
RP4 *4P2R-S-0RP4 *4P2R-S-0
2
4
1
3
C357 0.1U/10V/X5R_4C357 0.1U/10V/X5R_4
Y3
14.318MHZ
Y3
14.318MHZ
1 2
R146 EV@33_4R146 EV@33_4
QFN32
U7
9LVS3197
QFN32
U7
9LVS3197
VDD_CPU_IO
18
SATA
10
VDD_SRC_IO
15
VSS_USB
2
27MHz_SS
7
DOT96C_LPR
4
SRC-1
13
SRC-1#
14
SATA#
11
27MHz_nonSS
6
DOT96T_LPR
3
VSS_CPU
21
CPU-1
20
CPU-0#
22
CPU-0
23
VDD_LCD
5
VDD_SRC
17
VDD_CPU
24
VDD_USB
1
VSS_LCD
8
VSS_SRC
12
REF_0/CPU_SEL
30
CPU_STOP#
16
CPU-1#
19
VSS_REF
26
VDD_REF
29
XOUT
27
XIN
28
SCLK
32
SDATA
31
CK_PWRGD/PD#_3.3
25
GND
33
VSS_SATA
9
RP3 *4P2R-S-0RP3 *4P2R-S-0
2
4
1
3
C269 0.1U/10V/X5R_4C269 0.1U/10V/X5R_4
Q8
2N7002E
Q8
2N7002E
3
2
1
L18
*HCB1608KF-181T15_6
L18
*HCB1608KF-181T15_6
1 2
C223 4.7U/6.3V/X5R_6C223 4.7U/6.3V/X5R_6
C689 0.1U/10V/X5R_4C689 0.1U/10V/X5R_4
C252 *EV@10P/50V/C0G_4C252 *EV@10P/50V/C0G_4
R129 10K_4R129 10K_4
C250 *EV@10P/50V/C0G_4C250 *EV@10P/50V/C0G_4
RP5 *4P2R-S-0RP5 *4P2R-S-0
2
4
1
3
R137 33_4R137 33_4
C685 0.1U/10V/X5R_4C685 0.1U/10V/X5R_4
C224 4.7U/6.3V/X5R_6C224 4.7U/6.3V/X5R_6
C231 *10U/6.3V/X5R_8SC231 *10U/6.3V/X5R_8S
C287 0.1U/10V/X5R_4C287 0.1U/10V/X5R_4
C238
33P/50V/NPO_4
C238
33P/50V/NPO_4
12
R141
10K/F_4
R141
10K/F_4
R145 EV@33_4R145 EV@33_4
R131
1K/F_4
R131
1K/F_4
C471 0.1U/10V/X5R_4C471 0.1U/10V/X5R_4
C393 0.1U/10V/X5R_4C393 0.1U/10V/X5R_4
R138
*10K/F_4
R138
*10K/F_4
C253
*10P/50V/C0G_4
C253
*10P/50V/C0G_4
C240 0.1U/10V/X5R_4C240 0.1U/10V/X5R_4
C270 *0.047U/10V/X7R_4C270 *0.047U/10V/X7R_4
12
L17
HCB1608KF-181T15_6
L17
HCB1608KF-181T15_6
1 2
R127
100K/F_4
R127
100K/F_4
C208 *0.047U/10V/X7R_4C208 *0.047U/10V/X7R_4
12
RP6 *4P2R-S-0RP6 *4P2R-S-0
2
4
1
3
C227 0.1U/10V/X5R_4C227 0.1U/10V/X5R_4
C228 0.1U/10V/X5R_4C228 0.1U/10V/X5R_4
C242 4.7U/6.3V/X5R_6C242 4.7U/6.3V/X5R_6
hexainf@hotmail.com
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
PEG_RX#15
PEG_RX0
PEG_RX#11
PEG_RX#10
PEG_RX#8
PEG_RX#9
PEG_RBIAS
PEG_RX8
PEG_RX9
PEG_RX13
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX14
PEG_RX#14
PEG_COMP
PEG_RX#7
PEG_RX#2
PEG_RX#3
PEG_RX#1
PEG_RX#0
PEG_RX#6
PEG_RX#4
PEG_RX#5
PEG_RX15
PEG_RX#13
PEG_RX#12
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
H_PWRGOOD_1
H_VTTPWRGD
CPU_PLTRST#
SM_RCOMP_2
SM_RCOMP_0
SM_RCOMP_1
H_CATERR#
PM_EXT_TS#0
PM_EXT_TS#1
FDI_TXN2
FDI_TXN6
FDI_TXN7
FDI_TXN0
FDI_TXN1
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXP3
FDI_TXP4
FDI_TXP2
FDI_TXP0
FDI_TXP1
FDI_TXP6
FDI_TXP5
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
FDI_TXP7
DREFSSCLK#_R
DREFSSCLK_R
H_CPURST#
H_PWRGD_XDP
XDP_TDO_M
XDP_TDI_M
XDP_TDO_R
XDP_TDI_R
XDP_TRST#
XDP_TRST#
XDP_TCLK
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
XDP_TDI_R
XDP_PRDY#
XDP_PREQ#
XDP_OBS3
XDP_OBS2
XDP_OBS0
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
XDP_OBS1
BCLK_ITP_N
BCLK_ITP_P
PEG_TX#14
PEG_TX#9
PEG_TX#15
PEG_TX#10
PEG_TX#11
PEG_TX#1
PEG_TX#2
PEG_TX#12
PEG_TX#3
PEG_TX#4
PEG_TX#0
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#13
PEG_TX#8
C_PEG_TX#15
C_PEG_TX#0
C_PEG_TX#12
C_PEG_TX#9
C_PEG_TX#6
C_PEG_TX#3
C_PEG_TX#1
C_PEG_TX#13
C_PEG_TX#10
C_PEG_TX#7
C_PEG_TX#4
C_PEG_TX#2
C_PEG_TX#14
C_PEG_TX#11
C_PEG_TX#8
C_PEG_TX#5
PEG_TX14
PEG_TX9
PEG_TX15
PEG_TX11
PEG_TX1
PEG_TX2
PEG_TX12
PEG_TX3
PEG_TX4
PEG_TX0
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX13
PEG_TX8
PEG_TX10
C_PEG_TX15
C_PEG_TX0
C_PEG_TX12
C_PEG_TX9
C_PEG_TX6
C_PEG_TX3
C_PEG_TX1
C_PEG_TX13
C_PEG_TX10
C_PEG_TX7
C_PEG_TX4
C_PEG_TX2
C_PEG_TX14
C_PEG_TX11
C_PEG_TX8
C_PEG_TX5
H_COMP1
H_COMP2
H_COMP3
H_COMP0
HWPG
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
XDP_TMS
H_PROCHOT#
CPU_PLTRST#
H_CATERR#
PM_DRAM_PWRGD
DDR3_DRAMRST#_C
DDR3_DRAMRST#_C
HWPG_1 H_VTTPWRGD
HWPG_1
+1.5VCPU_PG
XDP_TMS
+1.5VCPU_PG
H_CPURST#
PEG_RX#[0..15] (15)
PEG_RX[0..15] (15)
DMI_TXN0(10)
DMI_TXN1(10)
DMI_TXN2(10)
DMI_TXN3(10)
DMI_TXP0(10)
DMI_TXP1(10)
DMI_TXP2(10)
DMI_TXP3(10)
DMI_RXN0(10)
DMI_RXN1(10)
DMI_RXN2(10)
DMI_RXN3(10)
DMI_RXP0(10)
DMI_RXP1(10)
DMI_RXP2(10)
DMI_RXP3(10)
PM_SYNC(10)
H_PWRGOOD(11)
PM_DRAM_PWRGD(10)
PLTRST#(9,15,23,27,28)
H_PECI(11)
H_PROCHOT#(40)
PM_THRMTRIP#(11)
+3V(3,8,9,10,11,12,13,14,15,20,21,22,24,25,26,27,28,29,30,31,32,33,35,36,40,41)
+1.5VSUS(6,13,14,35,37,41)
+1.05V_VTT(3,6,8,9,10,11,12,35,38,40,42)
PM_EXTTS#1 (14)
PM_EXTTS#0 (13)
FDI_TXN[7:0](10)
FDI_TXP[7:0](10)
FDI_FSYNC0(10)
FDI_INT(10)
FDI_LSYNC0(10)
FDI_LSYNC1(10)
FDI_FSYNC1(10)
DREFSSCLK# (9)
DREFSSCLK (9)
CLK_PCIE_3GPLL# (9)
CLK_PCIE_3GPLL (9)
XDP_DBRESET# (10)
PEG_TX#[0..15] (15)
PEG_TX[0..15] (15)
HWPG(11,30,37,38,39,40,42)
DDR3_DRAMRST# (13,14)
PCIE_CLK_REQ7# (11)
DELAY_VR_PWRGOOD(10,40)
DRAMRST_CTRL_EC (30)
+1.5VCPU_PG (37)
+3VS5(8,9,10,11,12,15,27,35)
+1.5VSUS_L(6,41)
CLK_CPU_BCLK (11)
CLK_CPU_BCLK# (11)
+1.05V_VTT
+1.05V_VTT
+3V
+1.05V_VTT
+1.5VSUS+3VS5
+3VS5
+1.5VSUS_L
+3VS5
+3VS5
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
4 42
C
PROCESSER 1/4(HOST&PEG)
Thursday, April 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
4 42
C
PROCESSER 1/4(HOST&PEG)
Thursday, April 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
4 42
C
PROCESSER 1/4(HOST&PEG)
Thursday, April 08, 2010
04
2.7GT/s data rate
FDI_FSYNC can
gang all these
4 signals
together and
tie them with
only one 1K
resistor to GND
( Check list
1.0 ).
Discrete Only
Rc
Ra
Rb
For ITP CLk
Rc 0 ohm NA
NA
0 ohm
Ra
Rb
DIS UMA
0 ohm
NA
Ra
Rb
Rc
Rd
Re
JTAG MAPPING
Scan Chain
(Default)
CPU Only
GMCH Only
STUFF -> Ra, Rc, Re
NO STUFF -> Rb, Rd
STUFF -> Ra, Rb
NO STUFF -> Rc, Rd, Re
STUFF -> Rd, Re
NO STUFF -> Ra, Rb, Rc
Use a voltage divider with VDDQ (1.5 V) rail
ON in S3) and resistor combination of 1.5K ±1%
(to VDDQ)/750±1% (to GND) to convert to
processor VTT level.
for S3 power reduction
For Calpella S3 power reduction
EC-C
EC-C
R521 24.9/F_4R521 24.9/F_4
T18T18
PCI EXPRESS -- GRAPHICS
DMI
Intel(R) FDI
U26A
IC,AUB_CFD_rPGA,R1P0
PCI EXPRESS -- GRAPHICS
DMI
Intel(R) FDI
U26A
IC,AUB_CFD_rPGA,R1P0
DMI_RX#[0]
A24
DMI_RX#[1]
C23
DMI_RX#[2]
B22
DMI_RX#[3]
A21
DMI_RX[0]
B24
DMI_RX[1]
D23
DMI_RX[2]
B23
DMI_RX[3]
A22
DMI_TX#[0]
D24
DMI_TX#[1]
G24
DMI_TX#[2]
F23
DMI_TX#[3]
H23
DMI_TX[0]
D25
DMI_TX[1]
F24
DMI_TX[3]
G23
DMI_TX[2]
E23
FDI_TX#[0]
E22
FDI_TX#[1]
D21
FDI_TX#[2]
D19
FDI_TX#[3]
D18
FDI_TX#[4]
G21
FDI_TX#[5]
E19
FDI_TX#[6]
F21
FDI_TX#[7]
G18
FDI_TX[0]
D22
FDI_TX[1]
C21
FDI_TX[2]
D20
FDI_TX[3]
C18
FDI_TX[4]
G22
FDI_TX[5]
E20
FDI_TX[6]
F20
FDI_TX[7]
G19
FDI_FSYNC[0]
F17
FDI_FSYNC[1]
E17
FDI_INT
C17
FDI_LSYNC[0]
F18
FDI_LSYNC[1]
D17
PEG_ICOMPI
B26
PEG_ICOMPO
A26
PEG_RBIAS
A25
PEG_RCOMPO
B27
PEG_RX#[0]
K35
PEG_RX#[1]
J34
PEG_RX#[2]
J33
PEG_RX#[3]
G35
PEG_RX#[4]
G32
PEG_RX#[5]
F34
PEG_RX#[6]
F31
PEG_RX#[7]
D35
PEG_RX#[8]
E33
PEG_RX#[9]
C33
PEG_RX#[10]
D32
PEG_RX#[11]
B32
PEG_RX#[12]
C31
PEG_RX#[13]
B28
PEG_RX#[14]
B30
PEG_RX#[15]
A31
PEG_RX[0]
J35
PEG_RX[1]
H34
PEG_RX[2]
H33
PEG_RX[3]
F35
PEG_RX[4]
G33
PEG_RX[5]
E34
PEG_RX[6]
F32
PEG_RX[7]
D34
PEG_RX[8]
F33
PEG_RX[9]
B33
PEG_RX[10]
D31
PEG_RX[11]
A32
PEG_RX[12]
C30
PEG_RX[13]
A28
PEG_RX[14]
B29
PEG_RX[15]
A30
PEG_TX#[0]
L33
PEG_TX#[1]
M35
PEG_TX#[2]
M33
PEG_TX#[3]
M30
PEG_TX#[4]
L31
PEG_TX#[5]
K32
PEG_TX#[6]
M29
PEG_TX#[7]
J31
PEG_TX#[8]
K29
PEG_TX#[9]
H30
PEG_TX#[10]
H29
PEG_TX#[11]
F29
PEG_TX#[12]
E28
PEG_TX#[13]
D29
PEG_TX#[14]
D27
PEG_TX#[15]
C26
PEG_TX[0]
L34
PEG_TX[1]
M34
PEG_TX[2]
M32
PEG_TX[3]
L30
PEG_TX[4]
M31
PEG_TX[5]
K31
PEG_TX[6]
M28
PEG_TX[7]
H31
PEG_TX[8]
K28
PEG_TX[9]
G30
PEG_TX[10]
G29
PEG_TX[11]
F28
PEG_TX[12]
E27
PEG_TX[13]
D28
PEG_TX[14]
C27
PEG_TX[15]
C25
T23T23
C615 EV@0.1U/10V/X5R_4C615 EV@0.1U/10V/X5R_4
C587 EV@0.1U/10V/X5R_4C587 EV@0.1U/10V/X5R_4
R73 49.9/F_4R73 49.9/F_4
U30
MC74VHC1G08DFT2G
U30
MC74VHC1G08DFT2G
2
1
4
3 5
R56 *0/J_4R56 *0/J_4
Q12
MMBT3904
Q12
MMBT3904
2
1 3
R480 *EV@0_4R480 *EV@0_4
T9T9
T24T24
R47 *68/J_4R47 *68/J_4
U31
*MC74VHC1G08DFT2G
U31
*MC74VHC1G08DFT2G
2
1
4
3 5
R108 1.5K/F_4R108 1.5K/F_4
C607 EV@0.1U/10V/X5R_4C607 EV@0.1U/10V/X5R_4
R64 56.2/F_4R64 56.2/F_4
C617 EV@0.1U/10V/X5R_4C617 EV@0.1U/10V/X5R_4
T20T20
R520 130/F_4R520 130/F_4
R75 20/F_4R75 20/F_4
T29T29
C609 EV@0.1U/10V/X5R_4C609 EV@0.1U/10V/X5R_4
R54 *51/J_4R54 *51/J_4
R467 0_4SR467 0_4S
R57 *0/J_4R57 *0/J_4
R90
2K/F_4
R90
2K/F_4
T25T25
C613 EV@0.1U/10V/X5R_4C613 EV@0.1U/10V/X5R_4
C594 EV@0.1U/10V/X5R_4C594 EV@0.1U/10V/X5R_4
Q13
PDTC143TT
Q13
PDTC143TT
1 3
2
R92 10K/J_4R92 10K/J_4
CLOCKS
MISC
THERMAL
DDR3
MISC
JTAG & BPM
PWR MANAGEMENT
U26B
IC,AUB_CFD_rPGA,R1P0
CLOCKS
MISC
THERMAL
DDR3
MISC
JTAG & BPM
PWR MANAGEMENT
U26B
IC,AUB_CFD_rPGA,R1P0
SM_RCOMP[1]
AM1
SM_RCOMP[2]
AN1
SM_DRAMRST#
F6
SM_RCOMP[0]
AL1
BCLK#
B16
BCLK
A16
BCLK_ITP#
AT30
BCLK_ITP
AR30
PEG_CLK#
D16
PEG_CLK
E16
DPLL_REF_SSCLK#
A17
DPLL_REF_SSCLK
A18
CATERR#
AK14
COMP3
AT23
PECI
AT15
PROCHOT#
AN26
THERMTRIP#
AK15
RESET_OBS#
AP26
VCCPWRGOOD_1
AN14
VCCPWRGOOD_0
AN27
SM_DRAMPWROK
AK13
VTTPWRGOOD
AM15
RSTIN#
AL14
PM_EXT_TS#[0]
AN15
PM_EXT_TS#[1]
AP15
PRDY#
AT28
PREQ#
AP27
TCK
AN28
TMS
AP28
TRST#
AT27
TDI
AT29
TDO
AR27
TDI_M
AR29
TDO_M
AP29
DBR#
AN25
BPM#[0]
AJ22
BPM#[1]
AK22
BPM#[2]
AK24
BPM#[3]
AJ24
BPM#[4]
AJ25
BPM#[5]
AH22
BPM#[6]
AK23
BPM#[7]
AH23
COMP2
AT24
PM_SYNC
AL15
TAPPWRGOOD
AM26
COMP1
G16
COMP0
AT26
SKTOCC#
AH24
C590 EV@0.1U/10V/X5R_4C590 EV@0.1U/10V/X5R_4
C596 EV@0.1U/10V/X5R_4C596 EV@0.1U/10V/X5R_4
R116 *0_4R116 *0_4
T10T10
C598 EV@0.1U/10V/X5R_4C598 EV@0.1U/10V/X5R_4
R485 *EV@0_4R485 *EV@0_4
C591 EV@0.1U/10V/X5R_4C591 EV@0.1U/10V/X5R_4
C589 EV@0.1U/10V/X5R_4C589 EV@0.1U/10V/X5R_4
T17T17
R78 20/F_4R78 20/F_4
C584 EV@0.1U/10V/X5R_4C584 EV@0.1U/10V/X5R_4
C586 EV@0.1U/10V/X5R_4C586 EV@0.1U/10V/X5R_4
R91 *0/short_4R91 *0/short_4
T21T21
T26T26
C619 EV@0.1U/10V/X5R_4C619 EV@0.1U/10V/X5R_4
R85 *EV@1K/F_4R85 *EV@1K/F_4
R132
10K_4
R132
10K_4
R93 10K/J_4R93 10K/J_4
R107 10K/F_4R107 10K/F_4
12
R482 0_4P2R_4R482 0_4P2R_4
2
4
1
3
Q7 BSS138_NLQ7 BSS138_NL
3
2
1
R105
*0_4
R105
*0_4
T15T15
C610 EV@0.1U/10V/X5R_4C610 EV@0.1U/10V/X5R_4
C606 EV@0.1U/10V/X5R_4C606 EV@0.1U/10V/X5R_4
C593 EV@0.1U/10V/X5R_4C593 EV@0.1U/10V/X5R_4
R86 *EV@1K/F_4R86 *EV@1K/F_4
T13T13
C592 EV@0.1U/10V/X5R_4C592 EV@0.1U/10V/X5R_4
R81 *EV@1K/F_4R81 *EV@1K/F_4
C597 EV@0.1U/10V/X5R_4C597 EV@0.1U/10V/X5R_4
C583 EV@0.1U/10V/X5R_4C583 EV@0.1U/10V/X5R_4
T27T27
R87 49.9/F_4R87 49.9/F_4
R82 *EV@1K/F_4R82 *EV@1K/F_4
R68 *0/J_4R68 *0/J_4
R134
10K_4
R134
10K_4
C581 EV@0.1U/10V/X5R_4C581 EV@0.1U/10V/X5R_4
C595 EV@0.1U/10V/X5R_4C595 EV@0.1U/10V/X5R_4
R100 *68/J_4R100 *68/J_4
T11T11T28T28
R63 *51/J_4R63 *51/J_4
R475 49.9/F_4R475 49.9/F_4
C616 EV@0.1U/10V/X5R_4C616 EV@0.1U/10V/X5R_4
R140
10K_4
R140
10K_4
R102 750/F_4R102 750/F_4
R122
100K/F_4
R122
100K/F_4
R527 100/F_4R527 100/F_4
R94 *0/short_4R94 *0/short_4
C585 EV@0.1U/10V/X5R_4C585 EV@0.1U/10V/X5R_4
R80 *EV@1K/F_4R80 *EV@1K/F_4
C265
1U/6.3V/X5R_4
C265
1U/6.3V/X5R_4
R88
1K/F_4
R88
1K/F_4
C582 EV@0.1U/10V/X5R_4C582 EV@0.1U/10V/X5R_4
C611 EV@0.1U/10V/X5R_4C611 EV@0.1U/10V/X5R_4
R59
51/J_4
R59
51/J_4
C614 EV@0.1U/10V/X5R_4C614 EV@0.1U/10V/X5R_4
C612 EV@0.1U/10V/X5R_4C612 EV@0.1U/10V/X5R_4
R66 *0/J_4R66 *0/J_4
C618 EV@0.1U/10V/X5R_4C618 EV@0.1U/10V/X5R_4
T19T19
C588 EV@0.1U/10V/X5R_4C588 EV@0.1U/10V/X5R_4
R53 *51/J_4R53 *51/J_4
R55
0/J_4
R55
0/J_4
T16T16
R522
*10K/F_4
R522
*10K/F_4
C205
0.047U/16V/X7R_4
C205
0.047U/16V/X7R_4
R465 *0_4R465 *0_4
R67 *51/J_4R67 *51/J_4
T14T14
R534
*8.25K/F_4
R534
*8.25K/F_4
R106
*0_4/S
R106
*0_4/S
C608 EV@0.1U/10V/X5R_4C608 EV@0.1U/10V/X5R_4
R103
750/F_4
R103
750/F_4
R89 49.9/F_4R89 49.9/F_4
R478 750/F_4R478 750/F_4
R104
1.5K/F_4
R104
1.5K/F_4
R533 *0_4R533 *0_4
R121 *0_4R121 *0_4
T12T12
T22T22
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
M_A_DM1
M_A_DM0
M_A_DM3
M_A_DM2
M_A_DM5
M_A_DM6
M_A_DM4
M_A_DM7
M_A_DQS#1
M_A_DQS#0
M_A_DQS#3
M_A_DQS#2
M_A_DQS#5
M_A_DQS#6
M_A_DQS#4
M_A_DQS#7
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS0
M_A_DQS4
M_A_DQS6
M_A_DQS5
M_A_DQS7
M_A_A1
M_A_A9
M_A_A10
M_A_A11
M_A_A8
M_A_A12
M_A_A15
M_A_A14
M_A_A13
M_A_A2
M_A_A3
M_A_A0
M_A_A5
M_A_A6
M_A_A7
M_A_A4
M_B_DQ2
M_B_DQ3
M_B_DQ34
M_B_DQ35
M_B_DQ37
M_B_DQ36
M_B_DQ39
M_B_DQ38
M_B_DQ32
M_B_DQ41
M_B_DQ40
M_B_DQ46
M_B_DQ47
M_B_DQ44
M_B_DQ45
M_B_DQ43
M_B_DQ42
M_B_DQ33
M_B_DQ53
M_B_DQ51
M_B_DQ50
M_B_DQ63
M_B_DQ62
M_B_DQ56
M_B_DQ57
M_B_DQ48
M_B_DQ54
M_B_DQ55
M_B_DQ52
M_B_DQ49
M_B_DQ58
M_B_DQ59
M_B_DQ61
M_B_DQ60
M_B_DQ6
M_B_DQ7
M_B_DQ4
M_B_DQ5
M_B_DQ0
M_B_DQ10
M_B_DQ11
M_B_DQ13
M_B_DQ12
M_B_DQ15
M_B_DQ14
M_B_DQ8
M_B_DQ9
M_B_DQ1
M_B_DQ18
M_B_DQ19
M_B_DQ21
M_B_DQ20
M_B_DQ23
M_B_DQ22
M_B_DQ16
M_B_DQ25
M_B_DQ24
M_B_DQ30
M_B_DQ31
M_B_DQ28
M_B_DQ29
M_B_DQ27
M_B_DQ26
M_B_DQ17
M_B_DQS#1
M_B_DQS#0
M_B_DQS#3
M_B_DQS#2
M_B_DQS#5
M_B_DQS#6
M_B_DQS#4
M_B_DQS#7
M_B_DQS1
M_B_DQS0
M_B_DQS3
M_B_DQS2
M_B_DQS5
M_B_DQS6
M_B_DQS4
M_B_DQS7
M_B_A1
M_B_A9
M_B_A10
M_B_A11
M_B_A8
M_B_A12
M_B_A15
M_B_A14
M_B_A13
M_B_A2
M_B_A3
M_B_A0
M_B_A5
M_B_A6
M_A_DQ2
M_B_A7
M_B_A4
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_B_DM1
M_B_DM0
M_B_DM3
M_B_DM2
M_B_DM5
M_B_DM6
M_B_DM4
M_B_DM7
M_A_DQ7
M_A_DQ10
M_A_DQ11
M_A_DQ13
M_A_DQ12
M_A_DQ14
M_A_DQ15
M_A_DQ8
M_A_DQ9
M_A_DQ0
M_A_DQ18
M_A_DQ19
M_A_DQ21
M_A_DQ20
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ31
M_A_DQ30
M_A_DQ28
M_A_DQ29
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ16
M_A_DQ17
M_A_DQ1
M_A_DQ34
M_A_DQ35
M_A_DQ37
M_A_DQ36
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ47
M_A_DQ46
M_A_DQ44
M_A_DQ45
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ32
M_A_DQ54
M_A_DQ52
M_A_DQ53
M_A_DQ51
M_A_DQ50
M_A_DQ58
M_A_DQ59
M_A_DQ61
M_A_DQ60
M_A_DQ62
M_A_DQ63
M_A_DQ56
M_A_DQ55
M_A_DQ49
M_A_DQ48
M_A_DQ57
M_A_DQ33
M_A_CLK1# (13)
M_A_CKE1 (13)
M_A_CLK1 (13)
M_A_DM[7:0] (13)
M_A_CS#0 (13)
M_A_CS#1 (13)
M_A_DQS#[7:0] (13)
M_A_ODT0 (13)
M_A_ODT1 (13)
M_A_DQS[7:0] (13)
M_A_A[15:0] (13)
M_A_CLK0 (13)
M_A_CLK0# (13)
M_A_CKE0 (13)
M_B_WE#(14)
M_B_RAS#(14)
M_B_CAS#(14)
M_B_DQ[63:0](14)
M_B_DQS#[7:0] (14)
M_B_DQS[7:0] (14)
M_B_CLK1# (14)
M_B_CKE1 (14)
M_B_CLK1 (14)
M_B_A[15:0] (14)
M_B_CLK0# (14)
M_B_CKE0 (14)
M_B_CLK0 (14)
M_B_CS#0 (14)
M_B_CS#1 (14)
M_B_ODT1 (14)
M_B_ODT0 (14)
M_B_DM[7:0] (14)
M_A_DQ[63:0](13)
M_A_BS#0(13)
M_A_WE#(13)
M_A_RAS#(13)
M_A_BS#1(13)
M_A_BS#2(13)
M_A_CAS#(13)
M_B_BS#1(14)
M_B_BS#2(14)
M_B_BS#0(14)
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
5 42
Custom
PROCESSER 2/4(DDR)
Thursday, April 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
5 42
Custom
PROCESSER 2/4(DDR)
Thursday, April 08, 2010
PROJECT : LL7A
Quanta Computer Inc.
RevSize
Date: Sheet of
Document Number
1A
5 42
Custom
PROCESSER 2/4(DDR)
Thursday, April 08, 2010
05
DM signals are not present on Clarkfield
processor. All DM signal can be left as
NC on Clarkfield and connect directly to
GND on So-DIMM side for Clarkfield
design only
DM signals are not present on Clarkfield
processor. All DM signal can be left as
NC on Clarkfield and connect directly to
GND on So-DIMM side for Clarkfield
design only
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)
DDR SYSTEM MEMORY B
U26D
IC,AUB_CFD_rPGA,R1P0
DDR SYSTEM MEMORY B
U26D
IC,AUB_CFD_rPGA,R1P0
SB_BS[0]
AB1
SB_BS[1]
W5
SB_BS[2]
R7
SB_CAS#
AC5
SB_RAS#
Y7
SB_WE#
AC6
SB_CK[0]
W8
SB_CK[1]
V7
SB_CK#[0]
W9
SB_CK#[1]
V6
SB_CKE[0]
M3
SB_CKE[1]
M2
SB_CS#[0]
AB8
SB_CS#[1]
AD6
SB_ODT[0]
AC7
SB_ODT[1]
AD1
SB_DM[0]
D4
SB_DM[1]
E1
SB_DM[2]
H3
SB_DM[3]
K1
SB_DM[4]
AH1
SB_DM[5]
AL2
SB_DM[6]
AR4
SB_DM[7]
AT8
SB_DQS[4]
AG2
SB_DQS#[4]
AH2
SB_DQS[5]
AL5
SB_DQS#[5]
AL4
SB_DQS[6]
AP5
SB_DQS#[6]
AR5
SB_DQS[7]
AR7
SB_DQS#[7]
AR8
SB_DQS[0]
C5
SB_DQS#[0]
D5
SB_DQS[1]
E3
SB_DQS#[1]
F4
SB_DQS[2]
H4
SB_DQS#[2]
J4
SB_DQS[3]
M5
SB_DQS#[3]
L4
SB_MA[0]
U5
SB_MA[1]
V2
SB_MA[2]
T5
SB_MA[3]
V3
SB_MA[4]
R1
SB_MA[5]
T8
SB_MA[6]
R2
SB_MA[7]
R6
SB_MA[8]
R4
SB_MA[9]
R5
SB_MA[10]
AB5
SB_MA[11]
P3
SB_MA[12]
R3
SB_MA[13]
AF7
SB_MA[14]
P5
SB_MA[15]
N1
SB_DQ[0]
B5
SB_DQ[1]
A5
SB_DQ[2]
C3
SB_DQ[3]
B3
SB_DQ[4]
E4
SB_DQ[5]
A6
SB_DQ[6]
A4
SB_DQ[7]
C4
SB_DQ[8]
D1
SB_DQ[9]
D2
SB_DQ[10]
F2
SB_DQ[11]
F1
SB_DQ[12]
C2
SB_DQ[13]
F5
SB_DQ[14]
F3
SB_DQ[15]
G4
SB_DQ[16]
H6
SB_DQ[17]
G2
SB_DQ[18]
J6
SB_DQ[19]
J3
SB_DQ[20]
G1
SB_DQ[21]
G5
SB_DQ[22]
J2
SB_DQ[23]
J1
SB_DQ[24]
J5
SB_DQ[25]
K2
SB_DQ[26]
L3
SB_DQ[27]
M1
SB_DQ[28]
K5
SB_DQ[29]
K4
SB_DQ[30]
M4
SB_DQ[31]
N5
SB_DQ[32]
AF3
SB_DQ[33]
AG1
SB_DQ[34]
AJ3
SB_DQ[35]
AK1
SB_DQ[36]
AG4
SB_DQ[37]
AG3
SB_DQ[38]
AJ4
SB_DQ[39]
AH4
SB_DQ[40]
AK3
SB_DQ[41]
AK4
SB_DQ[42]
AM6
SB_DQ[43]
AN2
SB_DQ[44]
AK5
SB_DQ[45]
AK2
SB_DQ[46]
AM4
SB_DQ[47]
AM3
SB_DQ[48]
AP3
SB_DQ[49]
AN5
SB_DQ[50]
AT4
SB_DQ[51]
AN6
SB_DQ[52]
AN4
SB_DQ[53]
AN3
SB_DQ[54]
AT5
SB_DQ[55]
AT6
SB_DQ[56]
AN7
SB_DQ[57]
AP6
SB_DQ[58]
AP8
SB_DQ[59]
AT9
SB_DQ[60]
AT7
SB_DQ[61]
AP9
SB_DQ[62]
AR10
SB_DQ[63]
AT10
DDR SYSTEM MEMORY A
U26C
IC,AUB_CFD_rPGA,R1P0
DDR SYSTEM MEMORY A
U26C
IC,AUB_CFD_rPGA,R1P0
SA_BS[0]
AC3
SA_BS[1]
AB2
SA_BS[2]
U7
SA_CAS#
AE1
SA_RAS#
AB3
SA_WE#
AE9
SA_CK[0]
AA6
SA_CK[1]
Y6
SA_CK#[0]
AA7
SA_CK#[1]
Y5
SA_CKE[0]
P7
SA_CKE[1]
P6
SA_CS#[0]
AE2
SA_CS#[1]
AE8
SA_ODT[0]
AD8
SA_ODT[1]
AF9
SA_DM[0]
B9
SA_DM[1]
D7
SA_DM[2]
H7
SA_DM[3]
M7
SA_DM[4]
AG6
SA_DM[5]
AM7
SA_DM[6]
AN10
SA_DM[7]
AN13
SA_DQS[0]
C8
SA_DQS#[0]
C9
SA_DQS[1]
F9
SA_DQS#[1]
F8
SA_DQS[2]
H9
SA_DQS#[2]
J9
SA_DQS[3]
M9
SA_DQS#[3]
N9
SA_DQS[4]
AH8
SA_DQS#[4]
AH7
SA_DQS[5]
AK10
SA_DQS#[5]
AK9
SA_DQS[6]
AN11
SA_DQS#[6]
AP11
SA_DQS[7]
AR13
SA_DQS#[7]
AT13
SA_MA[0]
Y3
SA_MA[1]
W1
SA_MA[2]
AA8
SA_MA[3]
AA3
SA_MA[4]
V1
SA_MA[5]
AA9
SA_MA[6]
V8
SA_MA[7]
T1
SA_MA[8]
Y9
SA_MA[9]
U6
SA_MA[10]
AD4
SA_MA[11]
T2
SA_MA[12]
U3
SA_MA[13]
AG8
SA_MA[14]
T3
SA_MA[15]
V9
SA_DQ[0]
A10
SA_DQ[1]
C10
SA_DQ[2]
C7
SA_DQ[3]
A7
SA_DQ[4]
B10
SA_DQ[5]
D10
SA_DQ[6]
E10
SA_DQ[7]
A8
SA_DQ[8]
D8
SA_DQ[9]
F10
SA_DQ[10]
E6
SA_DQ[11]
F7
SA_DQ[12]
E9
SA_DQ[13]
B7
SA_DQ[14]
E7
SA_DQ[15]
C6
SA_DQ[16]
H10
SA_DQ[17]
G8
SA_DQ[18]
K7
SA_DQ[19]
J8
SA_DQ[20]
G7
SA_DQ[21]
G10
SA_DQ[22]
J7
SA_DQ[23]
J10
SA_DQ[24]
L7
SA_DQ[25]
M6
SA_DQ[26]
M8
SA_DQ[27]
L9
SA_DQ[28]
L6
SA_DQ[29]
K8
SA_DQ[30]
N8
SA_DQ[31]
P9
SA_DQ[32]
AH5
SA_DQ[33]
AF5
SA_DQ[34]
AK6
SA_DQ[35]
AK7
SA_DQ[36]
AF6
SA_DQ[37]
AG5
SA_DQ[38]
AJ7
SA_DQ[39]
AJ6
SA_DQ[40]
AJ10
SA_DQ[41]
AJ9
SA_DQ[42]
AL10
SA_DQ[43]
AK12
SA_DQ[44]
AK8
SA_DQ[45]
AL7
SA_DQ[46]
AK11
SA_DQ[47]
AL8
SA_DQ[48]
AN8
SA_DQ[49]
AM10
SA_DQ[50]
AR11
SA_DQ[51]
AL11
SA_DQ[52]
AM9
SA_DQ[53]
AN9
SA_DQ[54]
AT11
SA_DQ[55]
AP12
SA_DQ[56]
AM12
SA_DQ[57]
AN12
SA_DQ[58]
AM13
SA_DQ[59]
AT14
SA_DQ[60]
AT12
SA_DQ[61]
AL13
SA_DQ[62]
AR14
SA_DQ[63]
AP14
hexainf@hotmail.com
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