5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEG_COMP
eDP_COMP
INT_eDP_HPD
PEG_RXN12
PEG_TXP1_C
PEG_TXP2_C
PEG_TXP3_C
PEG_TXP4_C
PEG_TXP5_C
PEG_TXP6_C
PEG_TXP7_C
PEG_TXP0_C
PEG_TXP8_C
PEG_TXP9_C
PEG_TXP10_C
PEG_TXP11_C
PEG_TXP12_C
PEG_TXP13_C
PEG_TXP14_C
PEG_TXP15_C
PEG_RXN13
PEG_TXP9
PEG_TXP14
PEG_TXP0
PEG_TXP3
PEG_TXP4
PEG_TXP15
PEG_RXN14
PEG_RXN15
PEG_TXN1_C PEG_TXN1
PEG_TXN4
PEG_TXN6
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN2_C
PEG_TXN3_C
PEG_TXN4_C
PEG_RXN1
PEG_TXN5_C
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP0
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_TXN6_C
PEG_RXN2
PEG_TXN7_C
PEG_RXN3
PEG_TXN0_C
PEG_RXN0
PEG_TXN8_C
PEG_RXN4
PEG_TXN9_C
PEG_RXN5
PEG_TXN10_C
PEG_RXN6
PEG_TXN11_C
PEG_RXN7
PEG_TXN12_C
PEG_RXN8
PEG_TXN13_C
PEG_RXN9
PEG_TXN14_C
PEG_RXN10
PEG_TXN15_C
PEG_RXN11
PEG_TXP6
PEG_TXP8
PEG_TXP1
PEG_TXN14
PEG_TXP5
PEG_TXP7
PEG_TXN15
PEG_TXP11
PEG_TXN8
PEG_TXN2
PEG_TXP2
PEG_TXN5
PEG_TXN13
PEG_TXP12
PEG_TXN3
PEG_TXN0
PEG_TXP10
PEG_TXP13
PEG_TXN7
eDP_COMP
INT_eDP_HPD
PEG_COMP
DMI_TXN09
DMI_TXN19
DMI_TXN29
DMI_TXN39
DMI_TXP09
DMI_TXP19
DMI_TXP29
DMI_TXP39
DMI_RXN09
DMI_RXN19
DMI_RXN29
DMI_RXN39
DMI_RXP09
DMI_RXP19
DMI_RXP29
DMI_RXP39
FDI_TXN09
FDI_TXN19
FDI_TXN39
FDI_TXN29
FDI_TXN59
FDI_TXN79
FDI_TXN69
FDI_TXN49
FDI_TXP19
FDI_TXP59
FDI_TXP79
FDI_TXP69
FDI_TXP49
FDI_TXP39
FDI_TXP29
FDI_TXP09
FDI_FSYNC09
FDI_FSYNC19
FDI_INT9
FDI_LSYNC19
FDI_LSYNC09
PEG_TXN[0..15] 18
PEG_TXP[0..15] 18
PEG_RXN[0..15] 18
PEG_RXP[0..15] 18
+1.05V_PCH
+1.05V_PCH
+1.05V_PCH
Size Document Number Rev
Date: Sheet of
Quanta Computer Inc.
PROJECT :
Sandy Bridge 1/5
1A
Wednesday, January 19, 2011
V02A/RO1A
4 61
Size Document Number Rev
Date: Sheet of
Quanta Computer Inc.
PROJECT :
Sandy Bridge 1/5
1A
Wednesday, January 19, 2011
V02A/RO1A
4 61
Size Document Number Rev
Date: Sheet of
Quanta Computer Inc.
PROJECT :
Sandy Bridge 1/5
1A
Wednesday, January 19, 2011
V02A/RO1A
4 61
Sandy Bridge Processor (DMI,PEG,FDI)
DP & PEG Compensation
PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
PEG_ICOMPO signals should
be routed within 500 mils
eDP_COMPIO and ICOMPO signals should
be shorted near balls and
routed within 500 mils
eDP_ICOMPO 12mil
eDP_COMPIO 4mil
PEG_ICOMPO 12mil
PEG_ICOMPI, PEG_RCOMPO 4mil,
Programing Disable eDP interface(BIOS)
eDP Hot-plug (Disable)
This signal can be left as no connect if
entire eDP interface is disabled.
CAD Note: Place PU resistor within 2 inches
of CPU
0.22uF AC coupling Caps for PCIE GEN1/2/3
C42 0.1U/10V_4C42 0.1U/10V_4
C27 0.1U/10V_4C27 0.1U/10V_4
C477 0.1U/10V_4C477 0.1U/10V_4
C488 0.1U/10V_4C488 0.1U/10V_4
C47 0.1U/10V_4C47 0.1U/10V_4
C38 0.1U/10V_4C38 0.1U/10V_4
C32 0.1U/10V_4C32 0.1U/10V_4
C40 0.1U/10V_4C40 0.1U/10V_4
C52 0.1U/10V_4C52 0.1U/10V_4
R20
*10K_4_NC
R20
*10K_4_NC
C470 0.1U/10V_4C470 0.1U/10V_4
C482 0.1U/10V_4C482 0.1U/10V_4
C45 0.1U/10V_4C45 0.1U/10V_4
C29 0.1U/10V_4C29 0.1U/10V_4
C46 0.1U/10V_4C46 0.1U/10V_4
R21 24.9/F_4R21 24.9/F_4
C44 0.1U/10V_4C44 0.1U/10V_4
C25 0.1U/10V_4C25 0.1U/10V_4
R47 24.9/F_4R47 24.9/F_4
C37 0.1U/10V_4C37 0.1U/10V_4
C26 0.1U/10V_4C26 0.1U/10V_4
C43 0.1U/10V_4C43 0.1U/10V_4
C481 0.1U/10V_4C481 0.1U/10V_4
C30 0.1U/10V_4C30 0.1U/10V_4
C478 0.1U/10V_4C478 0.1U/10V_4
C467 0.1U/10V_4C467 0.1U/10V_4
C24 0.1U/10V_4C24 0.1U/10V_4
C466 0.1U/10V_4C466 0.1U/10V_4
C471 0.1U/10V_4C471 0.1U/10V_4
C41 0.1U/10V_4C41 0.1U/10V_4
C36 0.1U/10V_4C36 0.1U/10V_4
C487 0.1U/10V_4C487 0.1U/10V_4
C35 0.1U/10V_4C35 0.1U/10V_4
C28 0.1U/10V_4C28 0.1U/10V_4
C33 0.1U/10V_4C33 0.1U/10V_4
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
U16A
CPU-989P-rPGA
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
U16A
CPU-989P-rPGA
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21
DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI
J22
PEG_ICOMPO
J21
PEG_RCOMPO
H22
PEG_RX#[0]
K33
PEG_RX#[1]
M35
PEG_RX#[2]
L34
PEG_RX#[3]
J35
PEG_RX#[4]
J32
PEG_RX#[5]
H34
PEG_RX#[6]
H31
PEG_RX#[7]
G33
PEG_RX#[8]
G30
PEG_RX#[9]
F35
PEG_RX#[10]
E34
PEG_RX#[11]
E32
PEG_RX#[12]
D33
PEG_RX#[13]
D31
PEG_RX#[14]
B33
PEG_RX#[15]
C32
PEG_RX[0]
J33
PEG_RX[1]
L35
PEG_RX[2]
K34
PEG_RX[3]
H35
PEG_RX[4]
H32
PEG_RX[5]
G34
PEG_RX[6]
G31
PEG_RX[7]
F33
PEG_RX[8]
F30
PEG_RX[9]
E35
PEG_RX[10]
E33
PEG_RX[11]
F32
PEG_RX[12]
D34
PEG_RX[13]
E31
PEG_RX[14]
C33
PEG_RX[15]
B32
PEG_TX#[0]
M29
PEG_TX#[1]
M32
PEG_TX#[2]
M31
PEG_TX#[3]
L32
PEG_TX#[4]
L29
PEG_TX#[5]
K31
PEG_TX#[6]
K28
PEG_TX#[7]
J30
PEG_TX#[8]
J28
PEG_TX#[9]
H29
PEG_TX#[10]
G27
PEG_TX#[11]
E29
PEG_TX#[12]
F27
PEG_TX#[13]
D28
PEG_TX#[14]
F26
PEG_TX#[15]
E25
PEG_TX[0]
M28
PEG_TX[1]
M33
PEG_TX[2]
M30
PEG_TX[3]
L31
PEG_TX[4]
L28
PEG_TX[5]
K30
PEG_TX[6]
K27
PEG_TX[7]
J29
PEG_TX[8]
J27
PEG_TX[9]
H28
PEG_TX[10]
G28
PEG_TX[11]
E28
PEG_TX[12]
F28
PEG_TX[13]
D27
PEG_TX[14]
E26
PEG_TX[15]
D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD
B16
eDP_ICOMPO
A17
