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COM.0 Re

PICMG® COM.0

COM Express™ Type 7 Preview

Purpose

The information in this document provides a preview of the upcoming PICMG® COM.0 COM Express®

Type 7 pinout. The pinout will officially launch with R3.0 of the specification later in 2016. The goal of

this document is to provide COM Express module and carrier designers with information on the soon to

be released Type 7 pinout so that potential users have the necessary design information.

Note: The information provided is preliminary and subject to change.

Why Type 7?

The current revision of the COM.0 specification was released 4 years ago. The interfaces provided in

the existing specification reflect the commonly used chipset interfaces at that time. In the last year

there has been an increased interest in higher bandwidth as well as additional Ethernet interfaces. The

primary motivation for Type 7 was to add support for two or four 10GbE interfaces.

Type 7

Type 7 is focused on data center applications where high bandwidth Ethernet interfaces are required.

Ideally the pins required for the new 10G signals would come from a pool of reserved pins.

Unfortunately, the COM.0 pinouts did not have the necessary number of pins available. Since most

data center applications are headless, the COM.0 subcommittee made the decision to repurpose the

video pins for 10GbE pins. The Type 7 pinout is based on Type 6 with the following changes:

 Removed LVDS, DDI, and VGA graphics interfaces. The pins now provide the 10G signals.

 Removed audio support. These pins are now reserved.

 Removed ExpressCard support. Some of these pins are now reserved.

 Reduced the number of SATA channels from 4 to 2 to gain 2 additional PCIe lanes.

 Reduced the number of USB 2.0 ports from 8 to 4 to gain 4 additional PCIe lanes. Note that all 4

USB ports support USB 3.0.

 Added 8 PCIe lanes for a total of up to 32.

 Added two or four 10GbE interfaces with management sideband signals.

 Added NC-SI interface.

 Added support for IEEE1588.

 Added eSPI interface multiplexed over LPC.

COM.0 Re

PICMG® COM.0

COM Express™ Type 7 Preview

Module 10GB Ethernet

Gigabit Ethernet

Type

Pwr Rail /

Tolerance

Description

PU/PD

Availability

10G_KR_TX[0:3]+

10G_KR_TX[0:3]-

O KR

AC coupled on

Carrier

10GBASE-KR ports, Transmit Output differential

pairs

10G_KR_RX[0:3]+

10G_KR_RX[0:3]-

I KR

AC coupled on

Module

10GBASE-KR ports, Receive Input differential

pairs

10G_PHY_MDIO_SDA[0:3]

3.3V Suspend /

3.3V

MDIO Mode Management Data I/O Interface

mode data signal for serial data transfers

between the MAC and an external PHY

I/O OD

3.3V Suspend /

3.3V

C Mode

C Data signal, of the 2-wire management

interface used for serial data transfers between

the MAC and an external PHY

PU 2K2

10G_PHY_MDC_SCL[0:3]

3.3V Suspend /

3.3V

MDIO Mode

Management Data I/O Interface mode clock

signal for serial data transfers between the

MAC and an external PHY

I/O OD

3.3V Suspend /

3.3V

C Mode

C Clock signal, of the 2-wire management

interface used for serial data transfers between

the MAC and an external PHY

PU 2K2

10G_SFP_SDA[0:3]

I/O OD

3.3V Suspend /

3.3V

I2C data signal of the 2-wire management

interface used by the 10GbE controller to

access the management registers of an

external Optical SFP module.

PU 2K2

10G_SFP_SCL[0:3]

I/O OD

3.3V Suspend /

3.3V

I2C clock signal of the 2-wire management

interface used by the 10GbE controller to

access the management registers of an

external Optical SFP module

PU 2K2

10G_LED_SDA

I/O OD

3.3V Suspend /

3.3V

I2C Data,of the 2-wire interface that transfers

all LED signals and additional Strapping Signal

for I2C or MDIO mode of the Optical PHY

PU 2K2

10G_LED_SCL

I/O OD

3.3V Suspend /

3.3V

I2C Clock,of the 2-wire interface that transfers

all LED signals and additional Strapping Signal

for I2C or MDIO mode of the Optical PHY

PU 2K2

10G_INT[0:3]

3.3V Suspend /

3.3V

Interrupt pin from Copper PHY or Optical SFP

module to the 10GbE Controller

PU 2K2

10G_SDP[0:3]

I/O

3.3V Suspend /

3.3V

Software-Definable Pins. Can also be used for

IEEE1588 support such as 1pps signal

10G_PHY_SEL_01

3.3V Suspend /

3.3V

Input signal that declares if the carrier board is

equipped with a Copper or Optical PHY on port

0 and port1. Default state is MDIO mode. For

I2C mode pull down with 1K on carrier

PU 10K

10G_PHY_SEL_23

3.3V Suspend /

3.3V

Input signal that declares if the carrier board is

equipped with a Copper or Optical PHY on port

2 and port 3. Default state is MDIO mode. For

I2C mode pull down with 1K on carrier

PU 10K

10G_PHY_RST_01

3.3V Suspend /

3.3V

Output signal that resets an Optical PHY

on port 0 and port1 (with Copper PHY this

signal is not used)

10G_PHY_RST_23

3.3V Suspend /

3.3V

Output signal that resets an Optical PHY

on port 2 and port 3 (with Copper PHY this

signal is not used)

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