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AD9954

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400 MSPS, 14-Bit, 1.8 V CMOS,

Direct Digital Synthesizer

Data Sheet

AD9954

Rev. C Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

400 MSPS internal clock speed

Integrated 14-bit DAC

Programmable phase/amplitude dithering

32-bit frequency tuning accuracy

14-bit phase tuning accuracy

Phase noise better than –120 dBc/Hz

Excellent dynamic performance

>80 dB narrowband SFDR

Serial input/output (I/O) control

Ultrahigh speed analog comparator

Automatic linear and nonlinear frequency sweeping

4 frequency/phase offset profiles

1.8 V power supply

Software and hardware controlled power-down

48-lead TQFP

Integrated 1024 word × 32-bit RAM

PLL-based REFCLK multiplier

Internal oscillator, can be driven by a single crystal

Phase modulation capability

Multichip synchronization

APPLICATIONS

Agile LO frequency synthesis

Programmable clock generators

FM chirp source for radar and scanning systems

Automotive radars

Test and measurement equipment

Acousto-optic device drivers

GENERAL DESCRIPTION

The AD9954 is a direct digital synthesizer (DDS) that uses

advanced technology, coupled with an internal high speed, high

performance DAC to form a complete, digitally programmable,

high frequency synthesizer capable of generating a frequency-

agile analog output sinusoidal waveform at up to 160 MHz.

The AD9954 enables fast frequency hopping coupled with fine

tuning of both frequency (0.01 Hz or better) and phase (0.022°

granularity).

The AD9954 is programmed via a high speed serial I/O port.

The device includes static RAM to support flexible frequency

sweep capability in several modes, plus a user-defined linear

sweep mode of operation. Also included is an on-chip high

speed comparator for applications requiring a square wave

output. An on-chip oscillator and PLL circuitry provide users

with multiple approaches to generate the device’s system clock.

The AD9954 is specified to operate over the extended industrial

temperature range (see Table 2).

BASIC BLOCK DIAGRAM

COMPARATOR

400MSPS

DDS CORE

14-BIT

DAC

REF CLOCK

INPUT CIRCUITRY

TIMING AND

CONTROL

DIGITA

SINE

WAVE

USER INTERFACE

AD9954

03374-038

Figure 1.

AD9954 Data Sheet

Rev. C | Page 2 of 40

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Basic Block Diagram ........................................................................ 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Electrical Specifications ................................................................... 4

Absolute Maximum Ratings ............................................................ 7

Explanation of Test Levels ........................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 13

Component Blocks ..................................................................... 13

Modes of Operation ................................................................... 16

Synchronization—Register Updates (I/O UPDATE) ............ 21

Serial Port Operation ................................................................. 23

Serial Interface Port Pin Descriptions ..................................... 24

MSB/LSB Transfers .................................................................... 24

RAM I/O via Serial Port ............................................................ 24

Instruction Byte .......................................................................... 25

Control Register Bit Descriptions ............................................ 29

Other Register Descriptions ..................................................... 31

Layout Considerations ............................................................... 32

Detailed Programming Examples ................................................ 33

Single-Tone Mode ...................................................................... 33

Linear Sweep Mode .................................................................... 33

RAM Mode.................................................................................. 33

Suggested Application Circuits ..................................................... 35

Evaluation Board Schematics........................................................ 36

Outline Dimensions ....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

2/2017

—Rev. B to Rev. C

Changes to Features Section............................................................ 1

5/2009—Re

v. A to Rev. B

Changes to Figure 29 and Figure 30 ............................................. 24

Changes to Table 12 ........................................................................ 26

Changes to Figure 34 ...................................................................... 35

Updated Outline Dimensions ....................................................... 39

Changes to Ordering Guide .......................................................... 39

1/2007—Rev. 0 to Rev. A

Changes to Layout .............................................................. Universal

Changes to Features, General Description, and Figure 1 ............ 1

Changes to Figure 2 .......................................................................... 3

Changes to Table 1 ............................................................................ 4

Changes to Table 4 ............................................................................ 8

Changes to Figure 5 to Figure 10 .................................................. 10

Changes to Figure 12 ...................................................................... 11

Changes to Figure 17 to Figure 18 Captions ............................... 12

Deleted Figure 19; Renumbered Sequentially............................. 12

Added Table 5; Renumbered Sequentially .................................. 13

Changes to Component Block Section and Table 6 ................... 13

Changes to Figure 20 ...................................................................... 15

Changes to Modes of Operation Section and Table 8 ............... 16

Changes to Table 9 .......................................................................... 17

Changes to Synchronization; Register Updates (I/O UPDATE)

Section and Figure 24..................................................................... 21

Changes to Serial Port Operation Section .................................. 23

Changes to Serial Interface Port Pin Description Section,

MSB/LSB Transfers Section, and RAM I/O Via Serial Port

Section .............................................................................................. 24

Inserted Figure 29 and Figure 30; Renumbered Sequentially .. 24

Changes to Instruction Byte Section, Register Maps and

Descriptions Section, and Table 12 .............................................. 25

Changes to Table 13 ....................................................................... 26

Changes to Table 14 ....................................................................... 28

Added Single-Tone Mode Section, Linear Sweep Mode Section,

Table 15, and RAM Mode Section ............................................... 33

Added, and Table 16 ....................................................................... 34

Inserted Figure 35 ........................................................................... 36

Inserted Figure 36 ........................................................................... 37

Inserted Figure 37 ........................................................................... 38

Updated Outline Dimensions ....................................................... 39

Changes to Ordering Guide .......................................................... 39

10/2003—Revision 0: Initial Version

AD9954 Data Sheet

Rev. C | Page 4 of 40

ELECTRICAL SPECIFICATIONS

Unless otherwise noted, AV DD,

DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R

SET

= 3.92 kΩ, external reference clock frequency =

400 MHz. DAC output must be referenced to AVDD, not AGND.

Table 1.

Parameter Temp

Test

Level

Min Typ Max Unit

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled Full VI 1 400 MHz

REFCLK Multiplier Enabled at 4× Full VI 20 100 MHz

REFCLK Multiplier Enabled at 20× Full VI 4 20 MHz

Crystal Oscillator Operating Frequency Full IV 20 30 MHz

Input Capacitance 25°C V 3 pF

Input Impedance 25°C V 1.5 kΩ

Duty Cycle 25°C V 50 %

Duty Cycle with REFCLK Multiplier Enabled

25°C

REFCLK Input Voltage Swing Full IV 100 1000 mV p-p

DAC OUTPUT CHARACTERISTICS

Full-Scale Output Current 25°C 5 10 15 mA

Gain Error 25°C I –10 +10 %FS

Output Offset 25°C I 0.6 µA

Differential Nonlinearity 25°C V 1 LSB

Integral Nonlinearity 25°C V 2 LSB

Output Capacitance 25°C V 5 pF

Residual Phase Noise @ 1 kHz Offset, 40 MHz A

OUT

REFCLK Multiplier Enabled @ 20× 25°C V –105 dBc/Hz

REFCLK Multiplier Enabled @ 4× 25°C V –115 dBc/Hz

REFCLK Multiplier Disabled 25°C V –132 dBc/Hz

Voltage Compliance Range 25°C I AVDD – 0.5 AVDD + 0.5 V

Wideband SFDR

1 MHz to 10 MHz Analog Out 25°C V 73 dBc

10 MHz to 40 MHz Analog Out 25°C V 67 dBc

40 MHz to 80 MHz Analog Out 25°C V 62 dBc

80 MHz to 120 MHz Analog Out 25°C V 58 dBc

120 MHz to 160 MHz Analog Out 25°C V 52 dBc

Narrow-Band SFDR

40 MHz Analog Out (±1 MHz) 25°C V 87 dBc

40 MHz Analog Out (±250 kHz) 25°C V 89 dBc

40 MHz Analog Out (±50 kHz) 25°C V 91 dBc

40 MHz Analog Out (±10 kHz) 25°C V 93 dBc

80 MHz Analog Out (±1 MHz) 25°C V 85 dBc

80 MHz Analog Out (±250 kHz) 25°C V 87 dBc

80 MHz Analog Out (±50 kHz) 25°C V 89 dBc

80 MHz Analog Out (±10 kHz) 25°C V 91 dBc

120 MHz Analog Out (±1 MHz) 25°C V 83 dBc

120 MHz Analog Out (±250 kHz) 25°C V 85 dBc

120 MHz Analog Out (±50 kHz)

25°C

dBc

120 MHz Analog Out (±10 kHz) 25°C V 89 dBc

160 MHz Analog Out (±1 MHz) 25°C V 81 dBc

160 MHz Analog Out (±250 kHz) 25°C V 83 dBc

160 MHz Analog Out (±50 kHz) 25°C V 85 dBc

160 MHz Analog Out (±10 kHz)

25°C

dBc

Data Sheet AD9954

Rev. C | Page 5 of 40

Parameter Temp

Test

Level Min Typ Max Unit

COMPARATOR INPUT CHARACTERISTICS

Input Capacitance 25°C V 3 pF

Input Resistance 25°C IV 500 kΩ

Input Current 25°C I ±12 µA

Hysteresis 25°C IV 30 45 mV

COMPARATOR OUTPUT CHARACTERISTICS

Logic 1 Voltage, High-Z Load Full VI 1.6 V

Logic 0 Voltage, High-Z Load Full VI 0.4 V

Propagation Delay 25°C IV 3 ns

Output Duty-Cycle Error 25°C IV ±5 %

Rise/Fall Time, 5 pF Load 25°C IV 1 ns

Toggle Rate, High-Z Load 25°C IV 200 MHz

Output Jitter

25°C IV 1 ps rms

COMPARATOR NARROW-BAND SFDR

10 MHz to 160 MHz F

OUT

Measured over a 1 MHz BW 25°C V 80 dBc

Measured over a 250 kHz BW 25°C V 85 dBc

Measured over a 50 kHz BW 25°C V 90 dBc

Measured over a 10 Hz BW 25°C V 95 dBc

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency

Full

Mbps

Minimum Clock Pulse Width Low Full IV 7 ns

Minimum Clock Pulse Width High Full IV 7 ns

Maximum Clock Rise/Fall Time Full IV 2 ns

Minimum Data Setup Time DVDD_I/O = 3.3 V Full IV 3 ns

Minimum Data Setup Time DVDD_I/O = 1.8 V Full IV 5 ns

Minimum Data Hold Time Full IV 0 ns

Maximum Data Valid Time Full IV 25 ns

Wake-Up Time

Full

Minimum Reset Pulse Width High Full IV 5 SYSCLK

cycles

I/O UPDATE, PS0, PS1 to SYNC_CLK Setup Time, DVDD_I/O = 3.3 V Full I 4 ns

I/O UPDATE, PS0, PS1 to SYNC_CLK Setup Time, DVDD_I/O = 1.8 V Full I 6 ns

I/O UPDATE, PS0, PS1 to SYNC_CLK Hold Time Full I 0 ns

Latency

I/O UPDATE to Frequency Change Prop Delay 25°C IV 24 SYSCLK

cycles

I/O UPDATE to Phase Offset Change Prop Delay 25°C IV 24 SYSCLK

cycles

I/O UPDATE to Amplitude Change Prop Delay 25°C IV 16 SYSCLK

cycles

PS0, PS1 to RAM Driven Frequency Change Prop Delay 25°C IV 28 SYSCLK

cycles

PS0, PS1 to RAM Driven Phase Change Prop Delay 25°C IV 28 SYSCLK

cycles

PS0 to Linear Frequency Sweep Prop Delay 25°C IV 28 SYSCLK

cycles

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