cordic用verilog实现

cordic算法的Verilog实现
283
module cordic
#(parameter DATA_WIDTH=8)
(
    input clk,
    input rst_n,
    input ena,
    input [DATA_WIDTH-1:0] phase_in,
    output reg [DATA_WIDTH-1:0] sin_out,
    output reg [DATA_WIDTH-1:0] cos_out,
    output reg [DATA_WIDTH-1:0] eps
);
 
localparam PIPELINE=8;
 
reg [DATA_WIDTH-1:0] phase_in_reg;
reg [DATA_WIDTH-1:0] x0,y0,z0;
reg [DATA_WIDTH-1:0] x1,y1,z1;
reg [DATA_WIDTH-1:0] x2,y2,z2;
reg [DATA_WIDTH-1:0] x3,y3,z3;
reg [DATA_WIDTH-1:0] x4,y4,z4;
reg [DATA_WIDTH-1:0] x5,y5,z5;
reg [DATA_WIDTH-1:0] x6,y6,z6;
reg [DATA_WIDTH-1:0] x7,y7,z7;
 
reg [1:0] quadrant [PIPELINE:0];
integer i;
 
always @(posedge clk,negedge rst_n)

begin
    if(!rst_n)
        phase_in_reg <= 8'b0;
    else
        if(ena)
        begin
            case(phase_in[7:6])
                2'b00: phase_in_reg <= phase_in;
                2'b01: phase_in_reg <= phase_in-8'h40;
                2'b10: phase_in_reg <= phase_in-8'h80;
                2'b11: phase_in_reg <= phase_in-8'hc0;
                default:;
            endcase
        end
end
 
always @ (posedge clk,negedge rst_n)
begin
    if(!rst_n)
        begin
            x0<=8'b0;
            y0<=8'b0;
            z0<=8'b0;
        end
    else
        if(ena)
        begin
            x0 <= 8'h4D;       //0.60725*2^7
            y0 <= 8'h00;
            z0 <= phase_in_reg;