-- Copyright (C) 1998-2005 Altera Corporation
--
-- File Name : EP1C3T144.BSD
-- Device : EP1C3T144
-- Package : 144-Pin Thin Quad Flat Pack
-- BSDL Version : 3.12
-- BSDL Status : Final
-- Date Created : 10/07/2004
-- Created by : Altera BSDL Generation Program Ver. 1.23
-- Verification : Software syntax checked on:
-- Agilent Technologies 3070 BSDL Compiler
-- ASSET ScanWorks ver. 3.1.1
-- Corelis ScanPlus TPG ver. 4.04
-- Genrad BSDL syntax checker ver. 4.01, a component
-- of Scan Pathfinder(tm) and BasicSCAN(tm)
-- GOEPEL Electronics' CASCON-GALAXY(R) ver. 4.03a
-- JTAG Technologies BSDL Converter ver. 3.2
--
-- Documentation : Cyclone Family Datasheet
-- AN39: JTAG Boundary Scan Testing for Altera Devices
--
-- *********************************************************************
-- * IMPORTANT NOTICE *
-- *********************************************************************
--
-- Altera, Cyclone and EP1C3 are trademarks of Altera
-- Corporation. Altera products, marketed under trademarks, are
-- protected under numerous US and foreign patents and pending
-- applications, maskwork rights, and copyrights. Altera warrants
-- performance of its semiconductor products to current specifications
-- in accordance with Altera's standard warranty, but reserves the
-- right to make changes to any products and services at any time
-- without notice. Altera assumes no responsibility or liability
-- arising out of the application or use of any information, product,
-- or service described herein except as expressly agreed to in
-- writing by Altera Corporation. Altera customers are advised to
-- obtain the latest version of device specifications before relying
-- on any published information and before placing orders for products
-- or services.
--
-- **Testing Differential Pin Pairs**
-- This file supports boundary scan testing (BST) before device
-- configuration. After configuration any pins that constitute part
-- of a differential pin pair are untestable; therefore, to perform
-- BST after configuration, the boundary scan cell (BSC) group
-- definitions that correspond to these differential pin pairs must
-- be edited. The bsc group should be redefined as an internal
-- cell. Make the following edits to this file:
-- a) Under the Entity Definitions With Ports section, change
-- the definition of the differential pins from inout bit, in
-- bit, or out bit to linkage bit.
-- b) Edit the corresponding bsc group definitions as shown in
-- the example below.
--
-- BSC group 278 for I/O pin H12
-- "834 (BC_1, IOH12, input, X)," &
-- "835 (BC_1, *, control, 1)," &
-- "836 (BC_1, IOH12, output3, X, 835, 1, Z)," &
--
-- Redefined as internal bsc group:
--
-- BSC group 278 for I/O pin H12
-- "834 (BC_4, *, internal, X)," &
-- "835 (BC_4, *, internal, 1)," &
-- "836 (BC_4, *, internal, X)," &
--
-- BSC groups for PLL_OUTp, PLL_OUTn, LVDSp, LVDSn,
-- LVDSCLKp, and LVDSCLKn pins will require the edits
-- listed above if differential signaling is used.
--
--
-- *********************************************************************
-- * ENTITY DEFINITION WITH PORTS *
-- *********************************************************************
entity EP1C3T144 is
generic (PHYSICAL_PIN_MAP : string := "TQFP144");
port (
--I/O Pins
IO1 , IO2 , IO3 , IO4 , IO5 , IO6 , IO7 ,
IO10 , IO11 , IO12 , IO25 , IO26 , IO27 , IO28 ,
IO31 , IO32 , IO33 , IO34 , IO35 , IO36 , IO37 ,
IO38 , IO39 , IO40 , IO41 , IO42 , IO47 , IO48 ,
IO49 , IO50 , IO51 , IO52 , IO53 , IO54 , IO55 ,
IO56 , IO57 , IO58 , IO59 , IO60 , IO61 , IO62 ,
IO67 , IO68 , IO69 , IO70 , IO71 , IO72 , IO73 ,
IO74 , IO75 , IO76 , IO77 , IO78 , IO79 , IO82 ,
IO83 , IO84 , IO85 , IO91 , IO94 , IO96 , IO97 ,
IO98 , IO99 , IO100 , IO103 , IO104 , IO105 , IO106 ,
IO107 , IO108 , IO109 , IO110 , IO111 , IO112 , IO113 ,
IO114 , IO119 , IO120 , IO121 , IO122 , IO123 , IO124 ,
IO125 , IO126 , IO127 , IO128 , IO129 , IO130 , IO131 ,
IO132 , IO133 , IO134 , IO139 , IO140 , IO141 , IO142 ,
IO143 , IO144 : inout bit;
--Cyclone Family-Specific Pins
CLK0 , CLK2 , DATA0 , MSEL0 ,
MSEL1 : in bit;
DCLK : inout bit;
CLK1 , CLK3 , CONF_DONE , NCE ,
NCEO , NCONFIG , NSTATUS : linkage bit;
--JTAG Ports
TCK , TMS , TDI : in bit;
TDO : out bit;
--Power Pins
VCC : linkage bit_vector (1 to 13);
--Ground Pins
GND : linkage bit_vector (1 to 14)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of EP1C3T144 :
entity is "STD_1149_1_1993";
-- *********************************************************************
-- * PIN MAPPING *
-- *********************************************************************
attribute PIN_MAP of EP1C3T144 : entity is PHYSICAL_PIN_MAP;
constant TQFP144 : PIN_MAP_STRING :=
--I/O Pins
"IO1 : 1 , IO2 : 2 , IO3 : 3 , IO4 : 4 , "&
"IO5 : 5 , IO6 : 6 , IO7 : 7 , IO10 : 10 , "&
"IO11 : 11 , IO12 : 12 , IO25 : 25 , IO26 : 26 , "&
"IO27 : 27 , IO28 : 28 , IO31 : 31 , IO32 : 32 , "&
"IO33 : 33 , IO34 : 34 , IO35 : 35 , IO36 : 36 , "&
"IO37 : 37 , IO38 : 38 , IO39 : 39 , IO40 : 40 , "&
"IO41 : 41 , IO42 : 42 , IO47 : 47 , IO48 : 48 , "&
"IO49 : 49 , IO50 : 50 , IO51 : 51 , IO52 : 52 , "&
"IO53 : 53 , IO54 : 54 , IO55 : 55 , IO56 : 56 , "&
"IO57 : 57 , IO58 : 58 , IO59 : 59 , IO60 : 60 , "&
"IO61 : 61 , IO62 : 62 , IO67 : 67 , IO68 : 68 , "&
"IO69 : 69 , IO70 : 70 , IO71 : 71 , IO72 : 72 , "&
"IO73 : 73 , IO74 : 74 , IO75 : 75 , IO76 : 76 , "&
"IO77 : 77 , IO78 : 78 , IO79 : 79 , IO82 : 82 , "&
"IO83 : 83 , IO84 : 84 , IO85 : 85 , IO91 : 91 , "&
"IO94 : 94 , IO96 : 96 , IO97 : 97 , IO98 : 98 , "&
"IO99 : 99 , IO100 : 100 , IO103 : 103 , IO104 : 104 , "&
"IO105 : 105 , IO106 : 106 , IO107 : 107 , IO108 : 108 , "&
"IO109 : 109 , IO110 : 110 , IO111 : 111 , IO112 : 112 , "&
"IO113 : 113 , IO114 : 114 , IO119 : 119 , IO120 : 120 , "&
"IO121 : 121 , IO122 : 122 , IO123 : 123 , IO124 : 124 , "&
"IO125 : 125 , IO126 : 126 , IO127 : 127 , IO128 : 128 , "&
"IO129 : 129 , IO130 : 130 , IO131 : 131 , IO132 : 132 , "&
"IO133 : 133 , IO134 : 134 , IO139 : 139 , IO140 : 140 , "&
"IO141 : 141 , IO142 : 142 , IO143 : 143 , IO144 : 144 , "&
--Cyclone Family-Specific Pins
"CLK0 : 16 , CLK2 : 93 , DATA0 : 13 , "&
"MSEL0 : 22 , MSEL1 : 23 , DCLK : 24 , "&
"CLK1 : 17 , CLK3 : 92 , CONF_DONE : 86 , "&
"NCE : 21 , NCEO : 20 , NCONFIG : 14 , "&
"NSTATUS : 87 , "&
--JTAG ports
"TCK : 88 , TMS : 89 , TDI : 95 , TDO : 90 , "&
--Power Pins
"VCC : (8 , 15 , 29 , 44 , 46 , 64 , 66 , 81 , "&
"102 , 115 ,
