/*
* nimu_eth.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/**
* @file nimu_eth.c
*
* @brief
* Ethernet Packet Driver rewritten using the NIMU Packet
* Architecture guidelines.
*
* Note: The NDK nimu driver interface is built based on the examples from the
* PDK. Please refer to PDK examples
* (<pdk_install_dir>\packages\ti\drv\pa\example\emacExample) directory to get
* the knowledge on the QMSS, CPPI, PA LLD configurations/programs.
*
*/
#include <ti/csl/csl_chipAux.h>
#include <ti/csl/csl_cpsgmiiAux.h>
#include <ti/csl/cslr_cpsgmii.h>
#include <ti/csl/csl_bootcfgAux.h>
#include <ti/transport/ndk/nimu/nimu_eth.h>
#include <ti/sysbios/family/c66/Cache.h>
#include "system/resource_mgr.h"
#include "nimu_internal.h"
/* The following code and define is used for code timing measurements of the Tx and Rx routines */
#ifdef TIMING
#include <ti/csl/csl_tsc.h>
#define MAX_TIMING_PACKETS 1000
#endif
#if NIMU_NUM_TX_DESC + NIMU_NUM_RX_DESC != 126
#error Sum of NIMU_NUM_TX_DESC and NIMU_NUM_RX_DESC must be same as defined in resource_mgr.h
#endif
#undef NIMU_NUM_TX_DESC
#undef NIMU_NUM_RX_DESC
#define NIMU_NUM_TX_DESC 48u /**< Maximum number of TX descriptors used by NIMU */
#define NIMU_NUM_RX_DESC 78u /**< Maximum number of RX descriptors used by NIMU */
/* nimu_debug: 0 -- close the debug info, 1 -- open the debug info */
int nimu_debug = 0;
/** @defgroup Platform_cache Platform Cache */
/*@{*/
/**
* @brief The following definitions are for handling cache alignment on the platform.
*
* MAX_CACHE_LINE must be set to the cache line size of the platform.
*
* When allocating memory that must be cache aligned, it must be a multiple of
* the cache line size. Use platform_roundup to get the appropriate size.
*
* As an example to allocate a cache aligned block of memory you would do
* something like:
*
* buffer_len_aligned = platform_roundup (buffer_len, MAX_CACHE_LINE)
* Malloc (buffer_len_aligned)
*
*/
/* w should be power of 2 */
#define PLATFORM_CACHE_LINE_SIZE (128)
#define platform_roundup(n,w) (((n) + (w) - 1) & ~((w) - 1))
#define MAX_CORES 8 /**< Maximum number of device cores */
#define PLATFORM_MAX_EMAC_PORT_NUM 2 /**< Maximum number of EMAC ports */
uint32_t coreKey [MAX_CORES];
/**
* @brief Indicates the EMAC port mode
*
*/
typedef enum {
PLATFORM_EMAC_PORT_MODE_NONE,
/**<EMAC port not used */
PLATFORM_EMAC_PORT_MODE_PHY,
/**<EMAC port connected to a PHY */
PLATFORM_EMAC_PORT_MODE_AMC,
/**<EMAC port connected to the backplane AMC chassis */
PLATFORM_EMAC_PORT_MODE_MAX
/**<End of port mode */
} PLATFORM_EMAC_PORT_MODE;
/**
* @brief This structure contains extended information about the EMAC
* e.g. port #, port mode, port MAC addess, etc.
*/
typedef struct {
uint32_t port_num;
/**<Port number of the EMAC port */
PLATFORM_EMAC_PORT_MODE mode;
/**<Mode of the EMAC port */
uint8_t mac_address[6];
/**<MAC address of the EMAC port */
} PLATFORM_EMAC_EXT_info;
/* This structure holds information about the EMAC port on the platform */
// #pragma DATA_SECTION(emac_port_mode,"platform_lib");
PLATFORM_EMAC_PORT_MODE emac_port_mode_nimu[PLATFORM_MAX_EMAC_PORT_NUM] =
{
PLATFORM_EMAC_PORT_MODE_AMC,
PLATFORM_EMAC_PORT_MODE_PHY
};
static UInt32 l2_global_address (Uint32 addr)
{
UInt32 corenum;
/* Get the core number. */
corenum = CSL_chipReadReg(CSL_CHIP_DNUM);
if((addr >= (uint32_t) 0x800000) && (addr < (uint32_t) 0x880000)) {
/* Compute the global address. */
return ((1 << 28) | (corenum << 24) | (addr & 0x00ffffff));
} else {
return addr;
}
}
/**
* @brief This function creates a delay from tscl
*
* @param cycles cycles for delay
*
* @return NULL
*/
static void cpu_delaycycles(uint32_t cycles)
{
uint32_t start_val;
start_val = CSL_chipReadTSCL();
while((CSL_chipReadTSCL() - start_val) < cycles);
return;
}
static int platform_get_emac_info(uint32_t port_num, PLATFORM_EMAC_EXT_info * emac_info)
{
uint32_t mac_addr2, mac_addr1;
emac_info->port_num = port_num;
emac_info->mode = emac_port_mode_nimu[port_num];
CSL_BootCfgGetMacIdentifier(&mac_addr1, &mac_addr2);
emac_info->mac_address[0] = ((mac_addr2 & 0x0000ff00) >> 8);
emac_info->mac_address[1] = (mac_addr2 & 0x000000ff);
emac_info->mac_address[2] = ((mac_addr1 & 0xff000000) >> 24);
emac_info->mac_address[3] = ((mac_addr1 & 0x00ff0000) >> 16);
emac_info->mac_address[4] = ((mac_addr1 & 0x0000ff00) >> 8);
emac_info->mac_address[5] = (mac_addr1 & 0x000000ff);
return 0;
}
/**
* @brief
* NIMUDeviceTable
*
* @details
* This is the NIMU Device Table for the Platform.
* This should be defined for each platform. Since the current platform
* has a single network Interface; this has been defined here. If the
* platform supports more than one network interface this should be
* defined to have a list of "initialization" functions for each of the
* interfaces.
*/
NIMU_DEVICE_TABLE_ENTRY NIMUDeviceTable[] =
{
/**
* @brief EmacInit for the platform
*/
EmacInit,
EmacInit,
NULL
};
/**
* @b EmacStart
* @n
* The function is used to initialize and start the EMAC
* controller and device.
*
* @param[in] ptr_net_device
* NETIF_DEVICE structure pointer.
*
* @retval
* Success - 0
* @retval
* Error - <0
*/
static int EmacStart
(
NETIF_DEVICE* ptr_net_device
)
{
EMAC_DATA* ptr_pvt_data;
paMacAddr_t broadcast_mac_addr = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
paEthInfo_t ethInfo = { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* Src mac = dont care */
{ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 }, /* Default Dest mac */
0, /* vlan = dont care */
0, /
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创龙Kintex7+TM320C6678资料.zip
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创龙Kintex7+TM320C6678资料.zip (971个子文件)
program_gui.bat 11KB
pdksetupenv.bat 9KB
pdkProjectCreate.bat 8KB
program.bat 4KB
convert.bat 456B
Build.bat 172B
tl_mig_dma_tlz7xh_xc7z100.bin 8.32MB
tl_aurora_dma_tlz7xh_xc7z100.bin 6.84MB
tl_mig_dma_tl6678f_xc7k325t.bin 6.5MB
tl_mig_dma_tlk7_xc7k325t.bin 6.5MB
tl_lvds_dma_tlz7xh_xc7z100.bin 6.44MB
tl_ibert_eyescan_tlz7xh_xc7z100.bin 4.62MB
tl_aurora_dma_tlk7_xc7k325t.bin 4.48MB
tl_aurora_dma_tl6678f_xc7k325t.bin 4.48MB
tl_mig_pcie_tlz7xh_xc7z100.bin 4.02MB
tl_ibert_eyescan_tlk7_xc7k325t.bin 3.59MB
tl_mig_dma_tla7_xc7a200t.bin 3.39MB
tl_bram_pcie_tlz7xh_xc7z100.bin 3.26MB
tl_bram_pcie_tlz7xh_xc7z100.bin 3.26MB
tl_lvds_dma_tl6678f_xc7k325t.bin 3.05MB
tl_mig_pcie_tlk7_xc7k325t.bin 3.02MB
tl_lvds_dma_tlk7_xc7k325t.bin 2.97MB
app.bin 2.89MB
app.bin 2.89MB
tl_fmc_ad9613_srio_tl6678f_xc7k325t.bin 2.77MB
tl_ibert_eyescan_tl6678f_xc7k325t.bin 2.7MB
tl_mig_dma_tl665xf_xc7a100t.bin 2.51MB
tl_mig_dma_tl5728f_xc7a100t.bin 2.46MB
tl_mig_dma_tla7_xc7a100t.bin 2.46MB
tl_aurora_dma_tla7_xc7a200t.bin 2.37MB
tl_bram_pcie_tlk7_xc7k325t.bin 2.32MB
tl_bram_pcie_tlk7_xc7k325t.bin 2.32MB
tl_lvds_dma_tla7_xc7a100t.bin 2.15MB
tl_lvds_dma_tl5728f_xc7a100t.bin 2.14MB
tl_fmc_ad9613_tlz7xh_xc7z100.bin 2.09MB
tl_lvds_dma_tla7_xc7a200t.bin 2.04MB
tl_lvds_dma_tl665xf_xc7a100t.bin 2.04MB
tl_bram_srio_target_tl6678f_xc7k325t.bin 2MB
tl_mig_pcie_tla7_xc7a100t.bin 1.92MB
tl_aurora_dma_tla7_xc7a100t.bin 1.86MB
tl_aurora_dma_tl665xf_xc7a100t.bin 1.84MB
tl_aurora_dma_tl5728f_xc7a100t.bin 1.59MB
tl_fmc_ad9613_tl6678f_xc7k325t.bin 1.52MB
tl_bram_pcie_tla7_xc7a100t.bin 1.52MB
tl_bram_pcie_tla7_xc7a100t.bin 1.52MB
tl_led_flash_tlz7xh_xc7z100.bin 1.52MB
tl_fmc_ad9613_tlk7_xc7k325t.bin 1.52MB
tl_key_test_tlz7xh_xc7z100.bin 1.52MB
C66x-le.bin 1.39MB
tl_ibert_eyescan_tl665xf_xc7a100t.bin 1.32MB
tl_ibert_eyescan_tl5728f_xc7a100t.bin 1.32MB
tl_ibert_eyescan_tla7_xc7a100t.bin 1.32MB
tl_bram_srio_target_tl665xf_xc7a100t.bin 1.26MB
tl_bram_emifa_tl6678f_xc7k325t.bin 1.08MB
tl_led_flash_tlk7_xc7k325t.bin 1012KB
tl_led_flash_tl6678f_xc7k325t.bin 1012KB
tl_key_test_tl6678f_xc7k325t.bin 1003KB
tl_key_test_tlk7_xc7k325t.bin 1003KB
tl_fmc_ad9613_tl5728f_xc7a100t.bin 785KB
tl_bram_emifa_tl665xf_xc7a100t.bin 413KB
tl_led_flash_tlz7x_xc7z020.bin 401KB
tl_key_test_tlz7x_xc7z020.bin 398KB
tl_key_test_tl665xf_xc7a100t.bin 372KB
tl_key_test_tla7_xc7a100t.bin 366KB
tl_led_flash_tla7_xc7a100t.bin 365KB
tl_led_flash_tl665xf_xc7a100t.bin 360KB
tl_key_test_tl5728f_xc7a100t.bin 357KB
tl_led_flash_tl5728f_xc7a100t.bin 355KB
tl_led_flash_tlz7x_xc7z010.bin 234KB
tl_key_test_tlz7x_xc7z010.bin 228KB
tl_aurora_dma_tlz7xh_ps.bin 96KB
tl_lvds_dma_tlz7xh_ps.bin 96KB
tl_mig_dma_tlz7xh_ps.bin 96KB
tl_mig_dma_tlz7xh_microblaze.bin 74KB
tl_lvds_dma_tlz7xh_microblaze.bin 70KB
tl_aurora_dma_tlz7xh_microblaze.bin 70KB
ibl.bin 47KB
ibl.bin 47KB
tl_mig_dma_tlz7xh_xc7z100.bit 8.32MB
tl_aurora_dma_tlz7xh_xc7z100.bit 6.84MB
tl_mig_dma_tl6678f_xc7k325t.bit 6.5MB
tl_mig_dma_tlk7_xc7k325t.bit 6.5MB
tl_lvds_dma_tlz7xh_xc7z100.bit 6.44MB
tl_ibert_eyescan_tlz7xh_xc7z100.bit 4.62MB
tl_aurora_dma_tl6678f_xc7k325t.bit 4.48MB
tl_aurora_dma_tlk7_xc7k325t.bit 4.48MB
tl_mig_pcie_tlz7xh_xc7z100.bit 4.02MB
tl_ibert_eyescan_tlk7_xc7k325t.bit 3.59MB
tl_mig_dma_tla7_xc7a200t.bit 3.39MB
tl_bram_pcie_tlz7xh_xc7z100.bit 3.26MB
tl_bram_pcie_tlz7xh_xc7z100.bit 3.26MB
tl_lvds_dma_tl6678f_xc7k325t.bit 3.05MB
tl_mig_pcie_tlk7_xc7k325t.bit 3.02MB
tl_lvds_dma_tlk7_xc7k325t.bit 2.97MB
tl_fmc_ad9613_srio_tl6678f_xc7k325t.bit 2.77MB
tl_fmc_ad9613_srio_tl6678f.bit 2.77MB
tl_ibert_eyescan_tl6678f_xc7k325t.bit 2.7MB
tl_mig_dma_tl665xf_xc7a100t.bit 2.51MB
tl_mig_dma_tla7_xc7a100t.bit 2.46MB
tl_mig_dma_tl5728f_xc7a100t.bit 2.46MB
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