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xilinx芯片解决PCIE DMA问题
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利用xilinx芯片内部的PCIE IP核完成设计
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DMA/Bridge Subsystem for
PCI Express v4.1
Product Guide
Vivado Design Suite
PG195 (v4.1) November 16, 2022
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information.
Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Features........................................................................................................................................4
IP Facts..........................................................................................................................................5
Chapter 2: Overview......................................................................................................6
Feature Summary........................................................................................................................8
Applications..................................................................................................................................8
Unsupported Features................................................................................................................9
Limitations....................................................................................................................................9
Licensing and Ordering............................................................................................................10
Chapter 3: Product Specification......................................................................... 12
Standards................................................................................................................................... 12
Performance and Resource Utilization...................................................................................12
Minimum Device Requirements..............................................................................................12
Configurable Components of the Subsystem........................................................................13
XDMA Operations......................................................................................................................19
Port Descriptions.......................................................................................................................30
Register Space........................................................................................................................... 43
Chapter 4: Designing with the Subsystem..................................................... 77
Clocking and Resets.................................................................................................................. 77
Tandem Configuration..............................................................................................................78
Chapter 5: Design Flow Steps.................................................................................83
Customizing and Generating the Subsystem........................................................................ 83
Constraining the Subsystem....................................................................................................95
Simulation.................................................................................................................................. 97
Synthesis and Implementation............................................................................................. 100
Chapter 6: Example Design................................................................................... 101
Available Example Designs.................................................................................................... 101
PG195 (v4.1) November 16, 2022 www.xilinx.com
DMA/Bridge Subsystem for PCIe 2
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Customizing and Generating the Example Design.............................................................111
Chapter 7: Test Bench...............................................................................................113
Root Port Model Test Bench for Endpoint............................................................................113
Appendix A: GT Locations.......................................................................................121
Appendix B: Application Software Development..................................... 122
Device Drivers..........................................................................................................................122
Linux Device Driver................................................................................................................. 123
Using the Driver...................................................................................................................... 123
Interrupt Processing...............................................................................................................123
Example H2C Flow...................................................................................................................124
Example C2H Flow...................................................................................................................125
Appendix C: Upgrading............................................................................................126
New Parameters......................................................................................................................126
New Ports.................................................................................................................................126
Appendix D: Debugging.......................................................................................... 129
Finding Help on Xilinx.com.................................................................................................... 129
Debug Tools............................................................................................................................. 130
Hardware Debug.....................................................................................................................131
Appendix E: Using the Xilinx Virtual Cable to Debug............................. 134
Overview...................................................................................................................................134
Host PC XVC-Server Application............................................................................................ 135
Host PC XVC-over-PCIe Driver............................................................................................... 135
XVC-over-PCIe Enabled FPGA Design................................................................................... 136
Using the PCIe-XVC-VSEC Example Design.......................................................................... 142
Appendix F: Additional Resources and Legal Notices............................151
Xilinx Resources.......................................................................................................................151
Documentation Navigator and Design Hubs...................................................................... 151
References................................................................................................................................151
Revision History.......................................................................................................................152
Please Read: Important Legal Notices................................................................................. 156
PG195 (v4.1) November 16, 2022 www.xilinx.com
DMA/Bridge Subsystem for PCIe 3
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Chapter 1
Introduction
The Xilinx
®
DMA/Bridge Subsystem for PCI Express
®
(PCIe
®
) implements a high performance,
congurable Scaer Gather DMA for use with the PCI Express
®
2.1 and 3.x Integrated Block.
The IP provides a choice between an AXI4 Memory Mapped or AXI4-Stream user interface.
This IP oponally also supports a PCIe AXI Bridge mode which is enabled for only UltraScale+™
devices. For details about PCIe AXI Bridge mode operaon, see AXI Bridge for PCI Express Gen3
Subsystem Product Guide (PG194).
This document covers DMA mode operaon only.
Note: For details about the Versal ACAP subsystem, refer to the Versal ACAP DMA and Bridge Subsystem for
PCI Express Product Guide (PG344).
Features
• Supports UltraScale+™, UltraScale™, Virtex
®
-7 XT Gen3 (Endpoint), and 7 series 2.1
(Endpoint) Integrated Blocks for PCIe. 7A15T and 7A25T are not supported
• Support for 64, 128, 256, 512-bit datapath (64, and 128-bit datapath only for 7 series Gen2
IP)
• 64-bit source, desnaon, and descriptor addresses
• Up to four host-to-card (H2C/Read) data channels (up to two for 7 series Gen2 IP)
• Up to four card-to-host (C2H/Write) data channels (up to two for 7 series Gen2 IP)
• Selectable user interface
○ Single AXI4 memory mapped (MM) user interface
○ AXI4-Stream user interface (each channel has its own AXI4-Stream interface)
• AXI4 Master and AXI4-Lite Master oponal interfaces allow for PCIe trac to bypass the
DMA engine
• AXI4-Lite Slave to access DMA status registers
• Scaer Gather descriptor list supporng unlimited list size
• 256 MB max transfer size per descriptor
Chapter 1: Introduction
PG195 (v4.1) November 16, 2022 www.xilinx.com
DMA/Bridge Subsystem for PCIe 4
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• Legacy, MSI, and MSI-X interrupts
• Block fetches of conguous descriptors
• Poll Mode
• Descriptor Bypass interface
• Arbitrary source and desnaon address
• Parity check or Propagate Parity on AXI bus (not available for 7 series Gen2 IP)
IP Facts
LogiCORE™ IP Facts Table
Subsystem Specifics
Supported Device Family
1
UltraScale+, UltraScale, 7 series Gen2 devices
Supported User Interfaces AXI4 MM, AXI4-Lite, AXI4-Stream
Resources See Resource Utilization web page.
Provided with Subsystem
Design Files Encrypted System Verilog
Example Design Verilog
Test Bench Verilog
Constraints File XDC
Simulation Model Verilog
Supported S/W Driver Linux and Windows Drivers
2
Tested Design Flows
3
Design Entry Vivado
®
Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado synthesis
Support
Release Notes and Known Issues Master Answer Record: AR 65443
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado
®
IP catalog.
2. For details, see Appendix B: Application Software Development and AR 65444.
3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
4. For Versal ACAP, refer to Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344).
Chapter 1: Introduction
PG195 (v4.1) November 16, 2022 www.xilinx.com
DMA/Bridge Subsystem for PCIe 5
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