RAM.rar_VHDL/FPGA/Verilog_VHDL_
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2021-08-11
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收藏 134KB RAR 举报
RAM.rar （70个子文件） 
dpram 
reg_dpram.pin 26KB reg_dpram.fit.smsg 513B reg_dpram.done 26B reg_dpram.qsf 3KB reg_dpram.fit.rpt 120KB reg_dpram.asm.rpt 7KB db logic_util_heursitic.dat 7KB prev_cmp_reg_dpram.qmsg 61KB reg_dpram.db_info 153B incremental_db compiled_partitions reg_dpram.db_info 153B README 653B reg_dpram.pof 512KB reg_dpram.map.rpt 21KB reg_dpram_nativelink_simulation.rpt 1001B reg_dpram.v 949B reg_dpram.sta.summary 657B reg_dpram.v.bak 753B reg_dpram.flow.rpt 9KB reg_dpram.map.summary 462B reg_dpram.qpf 1KB reg_dpram.sof 235KB reg_dpram.eda.rpt 6KB reg_dpram.fit.summary 604B reg_dpram.sta.rpt 84KB dqram dual.flow.rpt 6KB dual.vwf 17KB dual.pin 20KB dual.sof 148KB dual.fit.rpt 89KB dual.map.summary 452B dual.fit.smsg 513B dual.v 543B dual.fit.summary 590B db dual.sim.cvwf 2KB dual.sim.vwf 14KB prev_cmp_dual.tan.qmsg 39KB prev_cmp_dual.fit.qmsg 36KB prev_cmp_dual.eda.qmsg 3KB prev_cmp_dual.asm.qmsg 2KB wed.wsf 10KB altsyncram_vif1.tdf 12KB prev_cmp_dual.map.qmsg 13KB dual.db_info 153B prev_cmp_dual.sim.qmsg 3KB wed.zsf 122B prev_cmp_dual.qmsg 7KB dual.asm.rpt 7KB incremental_db compiled_partitions dual.root_partition.map.kpt 338B dual.db_info 153B README 653B dual.done 26B dual.eda.rpt 6KB dual.map.rpt 31KB simulation modelsim dual_modelsim.xrf 3KB dual.vo 37KB dual.sft 110B dual_v.sdo 15KB dual.tan.rpt 39KB dual.tan.summary 2KB dual.qpf 901B ddr_settings.dwz 316B RAM.v 1KB dual_nativelink_simulation.rpt 2KB dual_assignment_defaults.qdf 43KB dual.qws 1KB dual.qsf 2KB dual.sim.rpt 21KB dual.map.smsg 126B dual.v.bak 543B dual.pof 512KB资源评论
