Release 9.1i - par J.30
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Tue May 12 13:31:54 2015
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: last_map.ncd
OUTPUT FILE: last_pad.txt
PART TYPE: xc3s100e
SPEED GRADE: -5
PACKAGE: cp132
Pinout by Pin Number:
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|DCI Value|IO Register|Signal Integrity|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |PROG_B | | | | | | | | | | | | |
|A2 | | |TDI | | | | | | | | | | | | |
|A3 | |DIFFM |IO_L11P_0 |UNUSED | |0 | | | | | | | | | |
|A4 | | |NC | | | | | | | | | | | | |
|A5 | | |VCCAUX | | | | | | | |2.5 | | | | |
|A6 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|A7 |rst |IBUF |IO_L07P_0/GCLK10 |INPUT |LVCMOS25 |0 | | | |NONE | |LOCATED | |NO |NONE |
|A8 | | |GND | | | | | | | | | | | | |
|A9 | |DIFFS |IO_L05N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |
|A10 | |DIFFM |IO_L04P_0/GCLK4 |UNUSED | |0 | | | | | | | | | |
|A11 | | |VCCINT | | | | | | | |1.2 | | | | |
|A12 | | |NC | | | | | | | | | | | | |
|A13 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | |
|A14 | | |TDO | | | | | | | | | | | | |
|B1 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | | |
|B2 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | | |
|B3 | |DIFFS |IO_L11N_0/HSWAP |UNUSED | |0 | | | | | | | | | |
|B4 | |IBUF |IP |UNUSED | |0 | | | | | | | | | |
|B5 | |DIFFM |IO_L09P_0 |UNUSED | |0 | | | | | | | | | |
|B6 | |DIFFM |IO_L08P_0 |UNUSED | |0 | | | | | | | | | |
|B7 | |DIFFS |IO_L07N_0/GCLK11 |UNUSED | |0 | | | | | | | | | |
|B8 |clk |IBUF |IP_L06P_0/GCLK8 |INPUT |LVCMOS25 |0 | | | |NONE | |LOCATED | |NO |NONE |
|B9 | |DIFFM |IO_L05P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |
|B10 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |
|B11 | | |NC | | | | | | | | | | | | |
|B12 | | |NC | | | | | | | | | | | | |
|B13 | | |TCK | | | | | | | | | | | | |
|B14 | | |TMS | | | | | | | | | | | | |
|C1 | | |NC | | | | | | | | | | | | |
|C2 | |DIFFS |IO_L02N_3 |UNUSED | |3 | | | | | | | | | |
|C3 | |DIFFM |IO_L02P_3 |UNUSED | |3 | | | | | | | | | |
|C4 | | |NC | | | | | | | | | | | | |
|C5 | |DIFFS |IO_L09N_0 |UNUSED | |0 | | | | | | | | | |
|C6
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last.zip_VHDL/FPGA/Verilog_VHDL_
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vhd:57个
dat:57个
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verilog,FPGA的TDC电路设计
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last.zip_VHDL/FPGA/Verilog_VHDL_ (823个子文件)
__sdf1 214KB
__sdf1 189KB
__sdf2 214KB
__sdf2 189KB
_deps 34KB
_deps 23KB
_info 11KB
_opt1__lock 43B
_vmake 26B
tb.ant 3KB
tb.tfw.bak 2KB
last.bgn 4KB
last.bin 22KB
mux71.bin 6KB
shft1.bin 2KB
code73.bin 2KB
cnt.bin 2KB
dff5.bin 1KB
la.bin 983B
last.bit 71KB
last.bld 3KB
last.cel 0B
last.cmd_log 58KB
last_pad.csv 6KB
_primary.dat 631KB
_primary.dat 22KB
_primary.dat 10KB
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_primary.dat 782B
_primary.dat 268B
_primary.dat 176B
_primary.dbs 1.08MB
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