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云计算-基于FPGA的容错计算与通信验证平台.pdf
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云计算-基于FPGA的容错计算与通信验证平台.pdf
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2
ABSTRACT
Field Programmable Gate Array (FPGA) is widely applied to the aerospace field
with the advantages of high integration density, programmability and so on. The
commonly used anti-fuse FPGAs which have the problems of long development cost
and long development period, are gradually displaced by the Static Random Access
Memory (SRAM) FPGAs. This type of FPGAs has high intergration density, low cost
and is dynamically reconfigurable. However, the SRAM-based FPGAs are based on
the volatile memories. This structure is inherently sensitive to single event effects, in
the radiation environment, which limits their application. Single event upset (SEU) in
the memory of SRAM-based FPGA may change the designed circuit structure
completely, resulting in the system failure. In order to improve the possibility of
applications based on SRAM-based FPGAs in the radiation environment, it is
becoming a hot research about how to evaluate single event effect on design of the
circuit on the FPGAs.
Firstly, based on the basic structural characteristics of SRAM-based FPGAs and
the influence of single event upset on SRAM-based FPGAs, this thesis builds a
fault-tolerant computing and communication verification platform based on Virtex
Series FPGAs. The platform consists of the control unit, the fault-injection testing unit
and the reference unit. The control unit is the control center of the entire platform,
taking responsible for implementing the fault injection, results collection and so on.
The fault-injection testing unit is responsible for testing the circuit design on the
FPGAs with the fault injection of single event upset. The reference unit takes the
charge of providing the correct result of the same circuit design. The platform can
complete the tests to evaluate design sensitivity to single event upset quickly, using
the "sequential traversal" way, which can verify the feasibility of the fault tolerance
technologies which are implemented for reliable communication and computing
algorithms.
The implementation of this platform includes the design of hardware and
software. In the end of the thesis, the FPGA design of variable node processing unit in
low density parity check decoder is chose. The fault injection testing platform is used
3
to test the sensitive position in the design. Test results show that, this testing platform
for fault injection is effective.
KEY WORDS: FPGA, SEU, fault injection, partial reconfiguration
i
目 录
第一章 绪论..................................................................................................................1
1.1 研究背景和意义..............................................................................................1
1.2 研究现状与分析..............................................................................................2
1.2.1 卫星搭载试验........................................................................................2
1.2.2 地面辐射测试实验................................................................................2
1.2.3 故障注入实验........................................................................................3
1.3 论文主要工作及内容安排..............................................................................4
第二章 平台的方案设计..............................................................................................6
2.1 SRAM 型 FPGA 的优势和结构特点 ..............................................................6
2.2 SRAM 型 FPGA 的 SEU 概述.........................................................................8
2.2.1 SEU 产生机理 ........................................................................................8
2.2.2 SEU 对 SRAM 型 FPGA 的影响...........................................................8
2.3 平台的方案设计..............................................................................................9
2.3.1 故障注入方案......................................................................................10
2.3.2 平台工作流程......................................................................................11
2.4 本章小结........................................................................................................13
第三章 平台硬件的电路设计及实现........................................................................14
3.1 平台设计需求分析及硬件架构....................................................................14
3.2 电源模块........................................................................................................15
3.3 配置模块........................................................................................................16
3.3.1 Virtex 配置方案....................................................................................17
3.3.2 主串配置电路设计..............................................................................19
3.3.3 SelectMAP 配置电路设计 ...................................................................20
3.3.4 配置比特流文件转存电路设计..........................................................22
3.4 通信接口转换模块........................................................................................23
3.5 平台的电路实现............................................................................................25
3.6 本章小结........................................................................................................27
第四章 平台功能的实现与验证................................................................................28
4.1 平台功能总体架构设计................................................................................28
4.2 通信接口功能实现........................................................................................29
4.2.1 UART 接口工作原理 ...........................................................................29
ii
4.2.2 UART 功能实现 ...................................................................................29
4.3 命令解析功能实现........................................................................................31
4.4 从属 FPGA 配置数据存储功能实现............................................................31
4.4.1 并行 PROM 中数据的读取 ................................................................32
4.4.2 SRAM 读写时序 ..................................................................................32
4.4.3 SRAM 中配置数据的存取 ..................................................................34
4.5 从属 FPGA 配置功能实现............................................................................35
4.5.1 Virtex FPGA 的 SelectMAP 配置模式 ................................................35
4.5.2 SelectMAP 配置流程 ...........................................................................37
4.5.3 从属 FPGA 配置状态机的设计..........................................................38
4.6 故障注入功能实现........................................................................................38
4.6.1 FPGA 配置文件结构............................................................................39
4.6.2 配置数据寻址......................................................................................42
4.6.3 配置数据的修改与遍历......................................................................44
4.6.4 部分重构配置......................................................................................45
4.7 平台功能验证................................................................................................47
4.7.1 测试电路设计......................................................................................47
4.7.2 测试与结果分析..................................................................................48
4.8 本章小结........................................................................................................49
第五章 总结与展望....................................................................................................50
参考文献......................................................................................................................51
发表论文和参加科研情况说明..................................................................................56
致 谢......................................................................................................................57
第一章 绪论
1
第一章 绪论
1.1 研究背景和意义
卫星和航天器工作的宇宙空间中存在大量的高能粒子
[1, 2]
。这些高能粒子对
于空间仪器设备中半导体器件的影响称之为辐射效应。辐射效应会导致卫星和航
天器中部分电路功能出错,甚至造成整个电子系统永久失效。根据产生机理的不
同,辐射效应主要分为总剂量效应(Total Ionizing Dose,TID)和单粒子效应
(Single Event Effect,SEE)两大类
[3, 4]
。总剂量效应指半导体器件长时间处于
辐射环境中,由于高能粒子不断积累而产生的改变;单粒子效应指高能粒子射入
半导体器件后,由辐射效果立即作用所产生的改变。自 1975 年第一次发现由 SEE
导致的设备功能错误
[5]
以来,近 40 %的卫星失效是由空间环境的 SEE 引发
[6]
。
根据高能粒子入射情况的不同,半导体器件中所产生单粒子效应的具体情况
也不相同,主要包括单粒子瞬态(Single Event Transition,SET)、单粒子翻转
(Single Event Upset,SEU)、单粒子闩锁(Single Event Latch-up,SEL)和单粒
子功能中断(Single Event Function Interrupt,SEFI)等
[7]
,情况简述如表 1-1。表
1-2 是对 1971 年到 1986 年间 39 颗卫星发生故障情况的统计
[8]
,通过分析可以看
出单粒子效应中的单粒子翻转是引发卫星故障的最主要因素之一。
表 1-1 不同种类的 SEE 效应
[9]
缩略词 名称 情况简述
SET 单粒子瞬态效应 干扰电流的瞬时脉冲
SEU 单粒子翻转效应 电路节点逻辑状态的改变
SEL 单粒子闩锁效应 高电流状态、具有破坏性
SEFI 单粒子功能中断效应 电路逻辑运行状态中断
表 1-2 卫星故障发生情况数据统计
故障发生类型 故障发生次数 占总故障数的比例(%)
静电放电 215 13.53
电子诱发电磁脉冲 293 18.44
单粒子翻转 621 39.08
其它 460 28.95
总计 1589 100
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