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### FT232R USB to UART 接口芯片详解 #### 概述 FT232R 是由 Future Technology Devices International Ltd.（简称 FTDI）设计并制造的一款高性能 USB 到 UART 接口集成电路（IC）。这款芯片是 FTDI 产品线中的最新成员，集成了多种功能于一身，包括时钟信号发生器、FTDI Chip-ID 安全密钥功能以及 USB 到串行 UART 的转换接口。 #### 特点与优势 1. **单芯片 USB 至异步串行数据传输接口**：FT232R 能够实现 USB 与异步串行数据之间的转换，无需外部 EEPROM、时钟电路或 USB 电阻，简化了 USB 设计。 2. **完整的 USB 协议处理能力**：该芯片内置完整的 USB 协议处理逻辑，用户无需编写任何 USB 相关的固件代码即可实现 USB 通信。 3. **灵活的 UART 接口配置**：支持 7 或 8 位数据位、1 或 2 位停止位以及奇偶校验、标记、空格或无校验等多种配置选项。 4. **完善的硬件或软件握手机制**：支持全辅助硬件握手及 X-On/X-Off 软件握手，确保数据传输的稳定性和可靠性。 5. **高带宽数据传输**：数据传输速率最高可达 3 Mbps（在 RS422/RS485 和 TTL 水平下）和 1 Mbps（在 RS232 下）。 6. **大容量缓存设计**：拥有 256 字节接收缓冲区和 128 字节发送缓冲区，并采用缓存平滑技术，确保高效的数据吞吐量。 7. **免版权费的 VCP 和 D2XX 驱动程序**：FTDI 提供免版税的虚拟 COM 端口 (VCP) 和 D2XX 驱动程序，减少了大多数情况下开发 USB 驱动程序的需求。 8. **事件字符和行中断条件支持**：内置支持事件字符和行中断条件，增强了芯片的功能性和灵活性。 9. **创新的 FTDI Chip-ID 安全特性**：每个芯片在制造过程中都会被烧录一个独一无二的编号（FTDI Chip-ID），可通过 USB 读取，可用于保护客户的软件不被盗用或非法复制。 10. **可配置的 CBUS I/O 引脚**：新增了可配置的 CBUS 输入/输出引脚，增强了芯片的多功能性。 11. **自动发送缓冲区控制功能**：特别适用于 RS485 应用场合，能够自动控制发送缓冲区的状态。 12. **LED 驱动信号输出**：提供 LED 驱动信号，便于用户监控芯片的工作状态。 13. **广泛的封装选择**：FT232R 提供无铅（RoHS 合规）的紧凑型 28 引脚 SSOP 封装和 QFN-32 封装，适用于不同的应用需求。 #### 时钟信号发生器除了上述功能之外，FT232R 还具备内部产生的时钟信号（6 MHz、12 MHz、24 MHz 和 48 MHz）可以输出，用于驱动外部微控制器或其他逻辑器件。这一特性极大地扩展了芯片的应用范围。 #### 结论 FT232R 不仅是一款强大的 USB 到 UART 接口芯片，还具备时钟信号发生器、安全密钥等功能，使得它成为许多嵌入式系统设计的理想选择。无论是对于需要 USB 通信能力的项目，还是寻求增强安全性措施的应用场景，FT232R 都能提供卓越的性能和灵活性。

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Future Technology Devices International Ltd.

FT232R USB UART I.C.

Incorporating Clock Generator Output

and FTDIChip-ID™ Security Dongle

The FT232R is the latest device to be added to FTDI’s range of USB UART interface Integrated Circuit Devices. The

FT232R is a USB to serial UART interface with optional clock generator output, and the new FTDIChip-ID™ security

dongle feature. In addition, asynchronous and synchronous bit bang interface modes are available. USB to serial

designs using the FT232R have been further simpliﬁed by fully integrating the external EEPROM, clock circuit and

USB resistors onto the device.

The FT232R adds two new functions compared with its predecessors, effectively making it a “3-in-1” chip for some

application areas. The internally generated clock (6MHz, 12MHz, 24MHz, and 48MHz) can be brought out of the

device and used to drive a microcontroller or external logic. A unique number (the FTDIChip-ID™) is burnt into the

device during manufacture and is readable over USB, thus forming the basis of a security dongle which can be used

to protect customer application software from being copied.

The FT232R is available in Pb-free (RoHS compliant) compact 28-Lead SSOP and QFN-32 packages.

™

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 2

• Single chip USB to asynchronous serial data

transfer interface.

• Entire USB protocol handled on the chip - No

USB-speciﬁc ﬁrmware programming required.

• UART interface support for 7 or 8 data bits, 1 or 2

stop bits and odd / even / mark / space / no parity.

• Fully assisted hardware or X-On / X-Off software

handshaking.

• Data transfer rates from 300 baud to 3 Megabaud

(RS422 / RS485 and at TTL levels) and 300 baud

to 1 Megabaud (RS232).

• 256 byte receive buffer and 128 byte transmit

buffer utilising buffer smoothing technology to allow

for high data throughput.

• FTDI’s royalty-free VCP and D2XX drivers

eliminate the requirement for USB driver

development in most cases.

• In-built support for event characters and line break

condition.

• New USB FTDIChip-ID™ feature.

• New conﬁgurable CBUS I/O pins.

• Auto transmit buffer control for RS485 applications.

• Transmit and receive LED drive signals.

• New 48MHz, 24MHz,12MHz, and 6MHz clock

output signal Options for driving external MCU or

FPGA.

• FIFO receive and transmit buffers for high data

throughput.

• Adjustable receive buffer timeout.

• Synchronous and asynchronous bit bang mode

interface options with RD# and WR# strobes.

• New CBUS bit bang mode option.

• Integrated 1024 Bit internal EEPROM for storing

USB VID, PID, serial number and product

description strings, and CBUS I/O conﬁguration.

• Device supplied preprogrammed with unique USB

serial number.

• Support for USB suspend and resume.

• Support for bus powered, self powered, and high-

power bus powered USB conﬁgurations.

• Integrated 3.3V level converter for USB I/O .

• Integrated level converter on UART and CBUS for

interfacing to 5V - 1.8V Logic.

• True 5V / 3.3V / 2.8V / 1.8V CMOS drive output

and TTL input.

• High I/O pin output drive option.

• Integrated USB resistors.

• Integrated power-on-reset circuit.

• Fully integrated clock - no external crystal,

oscillator, or resonator required.

• Fully integrated AVCC supply ﬁltering - No separate

AVCC pin and no external R-C ﬁlter required.

• UART signal inversion option.

• USB bulk transfer mode.

• 3.3V to 5.25V Single Supply Operation.

• Low operating and USB suspend current.

• Low USB bandwidth consumption.

• UHCI / OHCI / EHCI host controller compatible

• USB 2.0 Full Speed compatible.

• -40°C to 85°C extended operating temperature

range.

• Available in compact Pb-free 28 Pin SSOP and

QFN-32 packages (both RoHS compliant).

1. Features

1.1 Hardware Features

Royalty-Free VIRTUAL COM PORT

(VCP) DRIVERS for...

• Windows 98, 98SE, ME, 2000, Server 2003, XP.

• Windows Vista / Longhorn*

• Windows XP 64-bit.*

• Windows XP Embedded.

• Windows CE.NET 4.2 & 5.0

• MAC OS 8 / 9, OS-X

• Linux 2.4 and greater

Royalty-Free D2XX Direct Drivers

(USB Drivers + DLL S/W Interface)

• Windows 98, 98SE, ME, 2000, Server 2003, XP.

• Windows Vista / Longhorn*

• Windows XP 64-bit.*

• Windows XP Embedded.

• Windows CE.NET 4.2 & 5.0

• Linux 2.4 and greater

1.2 Driver Support

The drivers listed above are all available to download for free from the FTDI website. Various 3rd Party Drivers are

also available for various other operating systems - see the FTDI website for details.

* Currently Under Development. Contact FTDI for availability.

• USB to RS232 / RS422 / RS485 Converters

• Upgrading Legacy Peripherals to USB

• Cellular and Cordless Phone USB data transfer

cables and interfaces

• Interfacing MCU / PLD / FPGA based designs to

USB

• USB Audio and Low Bandwidth Video data transfer

• PDA to USB data transfer

• USB Smart Card Readers

• USB Instrumentation

• USB Industrial Control

• USB MP3 Player Interface

• USB FLASH Card Reader / Writers

• Set Top Box PC - USB interface

• USB Digital Camera Interface

• USB Hardware Modems

• USB Wireless Modems

• USB Bar Code Readers

• USB Software / Hardware Encryption Dongles

1.3 Typical Applications

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 3

2. Enhancements

2.1 Device Enhancements and Key Features

This section summarises the enhancements and the key features of the FT232R device. For further details, consult

the device pin-out description and functional description sections.

Integrated Clock Circuit - Previous generations of FTDI’s USB UART devices required an external crystal or ceramic

resonator. The clock circuit has now been integrated onto the device meaning that no crystal or ceramic resonator is

required. However, if required, an external 12MHz crystal can be used as the clock source.

Integrated EEPROM - Previous generations of FTDI’s USB UART devices required an external EEPROM if the

device were to use USB Vendor ID (VID), Product ID (PID), serial number and product description strings other than

the default values in the device itself. This external EEPROM has now been integrated onto the FT232R chip meaning

that all designs have the option to change the product description strings. A user area of the internal EEPROM is

available for storing additional data. The internal EEPROM is programmable in circuit, over USB without any additional

voltage requirement.

Preprogrammed EEPROM - The FT232R is supplied with its internal EEPROM preprogrammed with a serial number

which is unique to each individual device. This, in most cases, will remove the need to program the device EEPROM.

Integrated USB Resistors - Previous generations of FTDI’s USB UART devices required two external series resistors

on the USBDP and USBDM lines, and a 1.5 kΩ pull up resistor on USBDP. These three resistors have now been

integrated onto the device.

Integrated AVCC Filtering - Previous generations of FTDI’s USB UART devices had a separate AVCC pin - the

supply to the internal PLL. This pin required an external R-C ﬁlter. The separate AVCC pin is now connected internally

to VCC, and the ﬁlter has now been integrated onto the chip.

Less External Components - Integration of the crystal, EEPROM, USB resistors, and AVCC ﬁlter will substantially

reduce the bill of materials cost for USB interface designs using the FT232R compared to its FT232BM predecessor.

Transmit and Receive Buffer Smoothing - The FT232R’s 256 byte receive buffer and 128 byte transmit buffer utilise

new buffer smoothing technology to allow for high data throughput.

Conﬁgurable CBUS I/O Pin Options - There are now 5 conﬁgurable Control Bus (CBUS) lines. Options are TXDEN

- transmit enable for RS485 designs, PWREN# - Power control for high power, bus powered designs, TXLED# - for

pulsing an LED upon transmission of data, RXLED# - for pulsing an LED upon receiving data, TX&RXLED# - which

will pulse an LED upon transmission OR reception of data, SLEEP# - indicates that the device going into USB

suspend mode, CLK48 / CLK24 / CLK12 / CLK6 - 48MHz, 24MHz,12MHz, and 6MHz clock output signal options.

There is also the option to bring out bit bang mode read and write strobes (see below). The CBUS lines can be

conﬁgured with any one of these output options by setting bits in the internal EEPROM. The device is supplied with

the most commonly used pin deﬁnitions preprogrammed - see Section 10 for details.

Enhanced Asynchronous Bit Bang Mode with RD# and WR# Strobes - The FT232R supports FTDI’s BM chip

bit bang mode. In bit bang mode, the eight UART lines can be switched from the regular interface mode to an 8-bit

general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface

at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the FT232R device this mode

has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used

to allow external logic to be clocked by accesses to the bit bang I/O bus. This option will be described more fully in a

separate application note.

Synchronous Bit Bang Mode - Synchronous bit bang mode differs from asynchronous bit bang mode in that the

interface pins are only read when the device is written to. Thus making it easier for the controlling program to measure

the response to an output stimulus as the data returned is synchronous to the output data. The feature was previously

seen in FTDI’s FT2232C device. This option will be described more fully in a separate application note.

CBUS Bit Bang Mode - This mode allows four of the CBUS pins to be individually conﬁgured as GPIO pins, similar

to Asynchronous bit bang mode. It is possible to use this mode while the UART interface is being used, thus providing

up to four general purpose I/O pins which are available during normal operation. An application note describing this

feature is available separately from the FTDI website.

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 4

Lower Supply Voltage - Previous generations of the chip required 5V supply on the VCC pin. The FT232R will work

with a Vcc supply in the range 3.3V - 5.25V. Bus powered designs would still take their supply from the 5V on the USB

bus, but for self powered designs where only 3.3V is available and there is no 5V supply there is no longer any need

for an additional external regulator.

Integrated Level Converter on UART Interface and Control Signals - VCCIO pin supply can be from 1.8V to 5V.

Connecting the VCCIO pin to 1.8V, 2.8V, or 3.3V allows the device to directly interface to 1.8V, 2.8V or 3.3V and other

logic families without the need for external level converter I.C. devices.

5V / 3.3V / 2.8V / 1.8V Logic Interface - The FT232R provides true CMOS Drive Outputs and TTL level Inputs.

Integrated Power-On-Reset (POR) Circuit- The device incorporates an internal POR function. A RESET# pin is

available in order to allow external logic to reset the FT232R where required. However, for many applications the

RESET# pin can be left unconnected, or pulled up to VCCIO.

Lower Operating and Suspend Current - The device operating supply current has been further reduced to 15mA,

and the suspend current has been reduced to around 70μA. This allows greater margin for peripheral designs to meet

the USB suspend current limit of 500μA.

Low USB Bandwidth Consumption - The operation of the USB interface to the FT232R has been designed to use

as little as possible of the total USB bandwidth available from the USB host controller.

High Output Drive Option - The UART interface and CBUS I/O pins can be made to drive out at three times the

standard signal drive level thus allowing multiple devices to be driven, or devices that require a greater signal drive

strength to be interfaced to the FT232R. This option is enabled in the internal EEPROM.

Power Management Control for USB Bus Powered, High Current Designs- The PWREN# signal can be used to

directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required.

An option in the internal EEPROM makes the device gently pull down on its UART interface lines when the power

is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND when power is

removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored.

UART Pin Signal Inversion - The sense of each of the eight UART signals can be individually inverted by setting

options in the internal EEPROM. Thus, CTS# (active low) can be changed to CTS (active high), or TXD can be

changed to TXD#.

FTDIChip-ID™ - Each FT232R is assigned a unique number which is burnt into the device at manufacture. This ID

number cannot be reprogrammed by product manufacturers or end-users. This allows the possibility of using FT232R

based dongles for software licensing. Further to this, a renewable license scheme can be implemented based on the

FTDIChip-ID™ number when encrypted with other information. This encrypted number can be stored in the user area

of the FT232R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-ID™ to verify

that a license is valid. Web based applications can be used to maintain product licensing this way. An application note

describing this feature is available separately from the FTDI website.

Improved EMI Performance - The reduced operating current and improved on-chip VCC decoupling signiﬁcantly

improves the ease of PCB design requirements in order to meet FCC, CE and other EMI related speciﬁcations.

Programmable Receive Buffer Timeout - The receive buffer timeout is used to ﬂush remaining data from the

receive buffer. This time defaults to 16ms, but is programmable over USB in 1ms increments from 1ms to 255ms, thus

allowing the device to be optimised for protocols that require fast response times from short data packets.

Extended Operating Temperature Range - The FT232R operates over an extended temperature range of -40º to

+85º C thus allowing the device to be used in automotive and industrial applications.

New Package Options - The FT232R is available in two packages - a compact 28 pin SSOP ( FT232RL) and an

ultra-compact 5mm x 5mm pinless QFN-32 package ( FT232RQ). Both packages are lead ( Pb ) free, and use a

‘green’ compound. Both packages are fully compliant with European Union directive 2002/95/EC.

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 5

3. Block Diagram

3.1 Block Diagram (Simpliﬁed)

Figure 1 - FT232R Block Diagram

3.2 Functional Block Descriptions

3.3V LDO Regulator - The 3.3V LDO Regulator generates the 3.3V reference voltage for driving the USB transceiver

cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It

also provides 3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of this block is to power

the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry

requiring a 3.3V nominal supply at a current of around than 50mA could also draw its power from the 3V3OUT pin, if

required.

USB Transceiver - The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB

cable. The output drivers provide 3.3V level slew rate control signalling, whilst a differential receiver and two single

ended receivers provide USB data in, SEO and USB Reset condition detection. This Cell also incorporates internal

USB series resistors on the USB data lines, and a 1.5kΩ pull up resistor on USBDP.

USB DPLL - The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and

data signals to the SIE block.

Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock input to the x4

Clock multiplier. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and

UART FIFO controller blocks

Clock Multiplier / Divider - The Clock Multiplier / Divider takes the 12MHz input from the Oscillator Cell and

generates the 48MHz, 24MHz, 12MHz, and 6MHz reference clock signals. The 48Mz clock reference is used for the

USB DPLL and the Baud Rate Generator blocks.

Clock

Multiplier /

Divider

UART

FIFO Controller

Serial Interface

Engine

( SIE )

USB

Protocol Engine

Baud Rate

Generator

UART Controller

with

Programmable

Signal Inversion

and High Drive

3.3 Volt

LDO

Regulator

USB

Transceiver

with

Integrated

Series

Resistors

and 1.5K

Pull-up

USB DPLL

Internal

12MHz

Oscillator

48MHz

OCSI

(optional)

OSCO

(optional)

USBDP

USBDM

3V3OUT

VCC

TXD

RXD

RTS#

CTS#

DTR#

DSR#

DCD#

RI#

CBUS0

CBUS2

CBUS3

RESET#

TEST

GND

RESET

GENERATOR

3V3OUT

CBUS1

FIFO TX Buffer

128 bytes

FIFO RX Buffer

256 bytes

Internal

EEPROM

To USB Transceiver Cell

CBUS4

24 MHz

12 MHz

6 MHz

To USB

Transceiver

Cell

VCCIO

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