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riscv boot Summit-bootflow.pdf
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2023-10-20
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riscv boot Summit_bootflow
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© 2019 Western Digital Corporation or its affiliates. All rights reserved. 12/19/19
An Introduction to RISC-V
Boot Flow
Atish Patra <Atish.Patra@wdc.com>
Anup Patel <Anup.Patel@wdc.com>
12/19/19© 2019 Western Digital Corporation or its affiliates. All rights reserved. 2
Outline
• Common embedded boot flow
• Current RISC-V boot flow
• OpenSBI Project
• Tutorials
• Current Status
• Future work
• Tutorials
12/19/19© 2019 Western Digital Corporation or its affiliates. All rights reserved. 3
Prerequisite
• Download the presentation
• Needs a Linux machine (Any distro will do)
• Linux Kernel source code build environment setup (optional)
• Instructions for Ubuntu
shorturl.at/clITU
sudo apt-get install git build-essential kernel-package fakeroot libncurses5-dev libssl-
dev bison flex
12/19/19© 2019 Western Digital Corporation or its affiliates. All rights reserved. 4
Getting started..
• Create a working directory
• Download cross-compiling toolchain
– https://toolchains.bootlin.com/releases_riscv64.html
• Download pre-built images
– https://wdc.box.com/s/ihywc2xap5m4mflyngjtndf0sy62zha3
• Clone OpenSBI
• Clone U-Boot
– ≈
shorturl.at/clITU
git clone https://github.com/riscv/opensbi.git
mkdir summit_demo; cd summit_demo
git clone https://github.com/u-boot/u-boot.git ; git checkout v2019.10
12/19/19© 2019 Western Digital Corporation or its affiliates. All rights reserved. 5
Common boot flow
Commonly used multiple boot stages model
ROM
LOADER
RUNTIME
BOOTLOADER OS
Loads
Jumps
• Runs from On-Chip
ROM
• Uses On-Chip SRAM
• SOC power-up and
clock setup
• DDR initialization
• Loads RUNTIME and
BOOTLOADER
• Examples:
• BIOS/UEFI
• U-Boot SPL
• Coreboot
• Runs from On-Chip SRAM or
DDR
• SOC security setup
• Runtime services as-per
specifications
• Examples:
• ATF
• BIOS/UEFI
• Runs from DDR
• Typically open-source
• Filesystem support
• Network booting
• Boot configuration
• Examples:
• U-Boot
• GRUB
• LinuxBoot
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