Codasip RISC-V 1&3&5 Series FPGA Platform Guide.pdf

Release Date February 18, 2022

1&3&5 SERIES FPGA PLATFORM

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Codasip 1&3&5 Series FPGA Platform

Copyright © 2017-2022 Codasip Group. All rights reserved.

Codasip, CodAL, Studio, CodeSpace, Bk Cores, and respective Bk core series are either the registered service marks, registered

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INTEGRATED 3RD PARTY SOFTWARE MODULES AND

TABLE OF CONTENTS

1 PREFACE 3

1.1 About 3

1.1.1 Intended Audience 3

1.1.2 Product Revisions 3

1.1.3 Typographical Conventions 3

1.1.4 Register Access Conventions 4

1.2 References 4

1.3 Feedback 4

1.3.1 Feedback on Codasip Products 4

3.3.1 Programming cables 6

3.3.2 Digilent NEXYS A7 7

3.3.3 Digilent NEXYS VIDEO 8

4 PLATFORMS OVERVIEW 9

4.1 Peripherals Configuration 9

4.1.1 GPIO 9

4.1.2 I2C 10

4.1.3 UART 10

4.1.4 QSPI 10

5 VIVADO PROJECT 11

6.1.5 I2C 14

6.1.6 Dhrystone 14

6.1.7 CoreMark 15

6.1.8 FreeRTOS 15

6.2 Compilation 15

6.3 Loading to the FPGA 16

7 PREPARING A CUSTOM ROM INITIALIZATION FILE 19

8 PERIPHERAL IP CORES 20

8.1 CLINT 20

8.1.1 Overview 20

8.2.3 Functional Description 23

8.2.4 Register Space 23

8.3 I2C 25

8.3.1 Overview 25

8.3.2 Port Description 25

8.3.3 Functional Description 26

8.3.4 Register Space 27

8.4 QSPI 32

8.4.1 Overview 32

8.4.2 Port Description 32

8.5.4 Register Space 40

9 ERRATA 49

9.1 CodeSpace reports false errors and warnings 49

9.1.1 Description 49

9.1.2 Workaround 49

1 PREFACE

1.1 About

By following the steps in this document, you will become familiar with the content of the Platforms package. By the end, you

will understand the features of the FPGA platform and will be able to run the provided demo applications on the FPGA

evaluation boards.

The Platforms package also contains documents and files from other packages provided by Codasip, such as Codasip RISC-V

Codasip CodeSpace v. 9.1.1