wrSbc8641d_AMP.rar

/* sysLib.c - Wind River SBC8641 system-dependent library */ /* * Copyright (c) 2007-2010, 2012, 2013 Wind River Systems, Inc. * * The right to copy, distribute, modify or otherwise make use * of this software may be licensed only pursuant to the terms * of an applicable Wind River license agreement. */ /* modification history -------------------- 01z,26jun13,d_l fix coverity errors. (WIND00423743) 01y,14nov12,d_l fix the AMP device filter. (WIND00387606) 01x,26aug10,liu change vxIpiEmit to vxIpiPhysEmit. (WIND00226567) 01w,19oct10,pch Ensure both CPUs' D-caches are flushed during SMP sysToMonitor() 01v,28jul10,liu allow to conditionnaly power management support. (WIND00185423) 01u,28jul10,liu flush L2 cache when reboot.(WIND00218322) 01t,10sep09,x_z Replace sysSvrGet() with vxSvrGet() of vxALib.s 01s,18nov08,pmr Fix WIND00137387: conditionalize BAT for upper memory 01r,12nov08,kab WIND00143297 - Fix build of CPU1 for gnu 01q,06nov08,pmr WIND00140224: shutdown ints on core1 for wrload 01p,23oct08,kab Update sysAmpCpuPrep to new sig per design mod 01o,16oct08,kab Add sysAmpCpuPrep() - wrload/multios support 01n,04sep08,dtr Add new sysAmpCpuStatusGet/Set calls. 01m,03sep08,dtr Switch to startcore to sysAmpCpuEnable. 01l,29aug08,kab Change _WRS_VX_SMP to _WRS_CONFIG_SMP 01k,11aug08,dtr Add wrload support. 01j,11jul08,to made vector area cacheable and coherent 01i,24apr08,dtr Remove hard coded IPI enable - WIND00121614. 01h,17apr08,to make BAT area not user-accessible 01g,25oct07,to added CPU1_INIT_START_ADR (WIND00107937) 01f,11sep07,h_k removed vxbIntToCpuRoute() call from sysCpuEnable(). (CQ:104081) 01e,04sep07,wap Add support for SMP (WIND00103522) 01d,30aug07,wap Switch to VxBus ETSEC and PCI drivers (WIND00103172) 01c,23aug07,pgh Fix apigen errors. 01b,30jul07,vik removed cmdLine.c inclusion 01a,20jun07,x_s initial creation. */ /* DESCRIPTION This library provides board-specific routines. The chip drivers included are: sysEpic.c - programmable interrupt controller driver sysDuart.c - duart controller config ns16550Sio.c - National Semiconductor 16550 UART driver ppcDecTimer.c - PowerPC decrementer timer library (system clock) flashMem.c - 29F040 flash memory device driver. altiVecLib.c - Altivec support for MPC 7400 sysCacheLib.s - L1 and L2 cache lock support INCLUDE FILES: sysLib.h SEE ALSO: .pG "Configuration" */ /* includes */ #include <stdio.h> #include <vxWorks.h> #include <vsbConfig.h> #include <vme.h> #include <memLib.h> #include <cacheLib.h> #include <sysLib.h> #include "config.h" #include <string.h> #include <intLib.h> #include <logLib.h> #include <taskLib.h> #include <vxLib.h> #include <tyLib.h> #include <vmLib.h> #include <arch/ppc/mmu603Lib.h> #include <arch/ppc/vxPpcLib.h> #ifdef INCLUDE_CACHE_L2 #include "sysL2Cache.h" #endif #ifdef INCLUDE_VXBUS #include <vxBusLib.h> #include <hwif/vxbus/vxBus.h> #endif #if defined INCLUDE_PCI_BUS #include <drv/pci/pciConfigLib.h> #include <drv/pci/pciAutoConfigLib.h> #include <drv/pci/pciIntLib.h> #endif #if defined (INCLUDE_ALTIVEC) #include <altivecLib.h> #endif #ifdef _WRS_CONFIG_SMP #include <private/kernelLibP.h> /* KERNEL_ENTERED_ME() */ #ifndef VX_CPC_ASYNC #define VX_CPC_ASYNC 2 typedef void (*CPC_FUNC) (void *, int); IMPORT void cpcInvoke (cpuset_t, CPC_FUNC, void *, int, int); #endif #endif #ifdef _WRS_VX_AMP #include <vxIpiLib.h> IMPORT int sysStartType; #endif /* _WRS_VX_AMP */ #ifdef INCLUDE_NV_RAM # include "eeprom.c" # include <mem/byteNvRam.c> /* Generic NVRAM routines */ #else # include <mem/nullNvRam.c> #endif /* INCLUDE_NV_RAM */ IMPORT int (* _func_altivecProbeRtn) () ; /* defines */ #define ZERO 0 #define SYS_MODEL "Wind River SBC8641D" /* globals */ /* * sysBatDesc[] is used to initialize the block address translation (BAT) * registers within the PowerPC 603/604 MMU. BAT hits take precedence * over Page Table Entry (PTE) hits and are faster. Overlap of memory * coverage by BATs and PTEs is permitted in cases where either the IBATs * or the DBATs do not provide the necessary mapping (PTEs apply to both * instruction AND data space, without distinction). * * The primary means of memory control for VxWorks is the MMU PTE support * provided by vmLib and cacheLib. Use of BAT registers will conflict * with vmLib support. Users may use BAT registers for i/o mapping and * other purposes but are cautioned that conflicts with caching and mapping * through vmLib may arise. Be aware that memory spaces mapped through a BAT * are not mapped by a PTE and any vmLib() or cacheLib() operations on such * areas will not be effective, nor will they report any error conditions. * * Note: BAT registers CANNOT be disabled - they are always active. * For example, setting them all to zero will yield four identical data * and instruction memory spaces starting at local address zero, each 128KB * in size, and each set as write-back and cache-enabled. Hence, the BAT regs * MUST be configured carefully. * * With this in mind, it is recommended that the BAT registers be used * to map LARGE memory areas external to the processor if possible. * If not possible, map sections of high RAM and/or PROM space where * fine grained control of memory access is not needed. This has the * beneficial effects of reducing PTE table size (8 bytes per 4k page) * and increasing the speed of access to the largest possible memory space. * Use the PTE table only for memory which needs fine grained (4KB pages) * control or which is too small to be mapped by the BAT regs. * * The BAT configuration for 4xx/6xx-based PPC boards is as follows: * All BATs point to PROM/FLASH memory so that end customer may configure * them as required. * * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments] */ UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT +_MMU_NUM_EXTRA_IBAT+_MMU_NUM_EXTRA_DBAT)] = { /* I BAT 0 */ ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS), ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT), /* I BAT 1 */ 0,0, /* I BAT 2 */ 0,0, /* I BAT 3 */ 0,0, /* D BAT 0 */ ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS), ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT), /* D BAT 1 */ ((CCSBAR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS), ((CCSBAR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 2 */ #ifdef _WRS_VX_AMP ((0x10000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_256M | _MMU_UBAT_VS), ((0x10000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_MEM_COHERENT), #else 0,0, #endif /* D BAT 3 */ 0,0 /* These entries are for the I/D BAT's (4-7) on the MPC7455/755. They should be defined in the following order. IBAT4U,IBAT4L,IBAT5U,IBAT5L,IBAT6U,IBAT6L,IBAT7U,IBAT7L, DBAT4U,DBAT4L,DBAT5U,DBAT5L,DBAT6U,DBAT6L,DBAT7U,DBAT7L, */ , /* I BAT 4 */ 0,0, /* I BAT 5 */ 0,0, /* I BAT 6 */ 0,0, /* I BAT 7 */ 0,0, /* D BAT 4 */ ((PERIPH_BASE & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS), ((PERIPH_BASE & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 5 */ ((0xf4000000 & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS), ((0xf4000000 & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED), /* D BAT 6 */ 0,0, /* D BAT 7 */ 0,0 }; /* * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array * used by the MMU to translate addresses with single page (4k) granularity. * PTE memory space should not, in general