L2 Cache Core Databook
PowerPC 476FP Preliminary
Contents
Page 4 of 188
Version 1.3
January 26, 2011
2.6.1.13 Data Write icbi, tlbivax, tlbsync ................................................................................. 45
2.6.1.14 Data Write dci .............................................................................................................. 45
2.7 Address Collisions ........................................................................................................................... 45
2.7.1 True Collisions ....................................................................................................................... 45
2.7.2 Speculative Collisions ............................................................................................................ 46
2.8 PLB6 (Snooper) Command Operation ............................................................................................ 47
2.8.1 Snoop Response Detailed Operation .................................................................................... 47
2.8.1.1 PLB6 Read, Read Atomic, RWNITC .............................................................................. 47
2.8.1.2 PLB6 RWITM .................................................................................................................. 47
2.8.1.3 PLB6 Clean .................................................................................................................... 47
2.8.1.4 PLB6 DClaim .................................................................................................................. 47
2.8.1.5 PLB6 Write with Kill ........................................................................................................ 48
2.8.1.6 PLB6 Write with Flush, Flush ......................................................................................... 48
2.8.1.7 PLB6 IKill ........................................................................................................................ 48
2.8.1.8 PLB6 MSync ................................................................................................................... 48
2.8.1.9 PLB6 MBar ..................................................................................................................... 48
2.8.1.10 PLB6 TLBIE .................................................................................................................. 48
2.8.1.11 PLB6 TLBSync ............................................................................................................. 49
2.9 L2 Cache Arrays .............................................................................................................................. 49
2.9.1 Array Configurations .............................................................................................................. 49
2.9.2 Array Addressing ................................................................................................................... 50
2.9.3 L2 Cache Array Layout .......................................................................................................... 52
2.9.3.1 Data Array ...................................................................................................................... 52
2.9.3.2 Tag Array ........................................................................................................................ 52
2.9.3.3 LRU Array ....................................................................................................................... 53
2.9.4 ECC Matrix ............................................................................................................................. 54
3. Hardware Interface .................................................................................................... 57
3.1 Clock, Reset, and Miscellaneous Interface ..................................................................................... 57
3.1.1 Clocks .................................................................................................................................... 58
3.1.2 Resets .................................................................................................................................... 58
3.1.3 Performance Counter Events ................................................................................................. 59
3.2 CPU Interfaces ................................................................................................................................ 60
3.2.1 Miscellaneous Interface ......................................................................................................... 60
3.2.2 L1 Cache MMU Interface ....................................................................................................... 61
3.2.3 L1 I-Cache Interface .............................................................................................................. 61
3.2.4 L1 D-Cache Interface ............................................................................................................. 62
3.3 PLB6 Interfaces ............................................................................................................................... 63
3.3.1 PLB6 Master Interface ........................................................................................................... 63
3.3.2 PLB6 Snoop Interface ............................................................................................................ 65
3.4 DCR Interface .................................................................................................................................. 66
4. Software Interface ..................................................................................................... 67
4.1 Initialization ...................................................................................................................................... 67
4.2 Reset ............................................................................................................................................... 68
4.3 CPU Sleep Mode ............................................................................................................................. 69
4.4 Registers Overview ......................................................................................................................... 69
4.4.1 Error Registers ....................................................................................................................... 70
4.4.2 Log Registers ......................................................................................................................... 72
