################################################################################
# Vivado (TM) v2018.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA远程更新工程(内含仿真文件) (756个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 20KB
xsim.ini.bak 20KB
xsim.ini.bak 20KB
implement_synplify.bat 3KB
implement.bat 3KB
simulate_ncsim.bat 3KB
simulate_ncsim.bat 3KB
simulate_vcs.bat 3KB
simulate_isim.bat 3KB
simulate_vcs.bat 3KB
simulate_isim.bat 3KB
planAhead_ise.bat 3KB
simulate_mti.bat 2KB
simulate_mti.bat 2KB
elaborate.bat 988B
compile.bat 964B
elaborate.bat 961B
elaborate.bat 902B
elaborate.bat 901B
simulate.bat 900B
simulate.bat 894B
simulate.bat 861B
simulate.bat 857B
compile.bat 836B
compile.bat 836B
compile.bat 836B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
GOLDEN_7K325.bin 2.09MB
GOLDEN_7K325.bit 2.09MB
coregen.cgp 236B
xsim.dbg 144KB
GOLDEN_7K325_routed.dcp 5.93MB
GOLDEN_7K325_placed.dcp 5.19MB
GOLDEN_7K325_opt.dcp 3.41MB
u_ila_0.dcp 1.9MB
dbg_hub.dcp 320KB
GOLDEN_7K325.dcp 216KB
fifo_w8d512.dcp 106KB
fifo_w8d512.dcp 106KB
fifo_w8d512.dcp 106KB
FPGA_BRAM.dcp 94KB
FPGA_BRAM.dcp 94KB
PLL.dcp 8KB
PLL.dcp 8KB
PLL.dcp 8KB
wave_mti.do 4KB
wave_mti.do 4KB
simulate_mti.do 3KB
simulate_mti.do 3KB
compile.do 1KB
compile.do 1023B
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compile.do 789B
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compile.do 739B
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simulate.do 341B
simulate.do 338B
simulate.do 338B
simulate.do 333B
simulate.do 328B
simulate.do 328B
simulate.do 299B
simulate.do 288B
simulate.do 288B
elaborate.do 213B
elaborate.do 205B
simulate.do 199B
simulate.do 195B
simulate.do 183B
elaborate.do 171B
wave.do 32B
wave.do 32B
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wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
simulate.do 11B
远程更新调试报告.docx 571KB
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