QUICC Engine Block Reference Manual with Protocol Interworking

1.1 QUICC Engine Block Overview ..................................................................................... 1-3

1.1.1 Protocols ...................................................................................................................... 1-8

1.1.2 Serial Interfaces ........................................................................................................... 1-9

1.1.3 Serial Protocol Table.................................................................................................... 1-9

1.3.4 WAN Gateway ........................................................................................................... 1-16

1.3.5 Additional Protocols .................................................................................................. 1-16

1.4 Overview of Interworking Flows and Protocol Stacks .................................................. 1-17

1.4.1 High Level Data Flows .............................................................................................. 1-17

1.4.2 Protocol Stacks .......................................................................................................... 1-18

1.4.2.1 Ethernet.................................................................................................................. 1-18

1.4.2.2 ML/MC PPP and PPPMux .................................................................................... 1-19

1.4.2.3 ATM....................................................................................................................... 1-19

1.4.2.3.1 AAL2 SSSAR.................................................................................................... 1-19

1.4.2.3.2 AAL5 RFC 2684, RFC 2364............................................................................. 1-20

1.4.3.4 ATM to Ethernet .................................................................................................... 1-23

1.4.3.4.1 AAL2 SSSAR to Ethernet ................................................................................. 1-23

1.4.3.4.2 AAL5 to Ethernet—Example 1 ......................................................................... 1-24

1.4.3.4.3 AAL5 to Ethernet—Example 2 ......................................................................... 1-25

1.4.3.5 ML/MC PPP with PPPMux over TDM links to Ethernet...................................... 1-26

1.5 Summary........................................................................................................................ 1-27

3.1 Serial DMA...................................................................................................................... 3-2

3.1.1 Data Paths .................................................................................................................... 3-3

3.1.4.2 Arbitration Over the Secondary Bus...................................................................... 3-12

3.1.4.3 Arbitration Over the Multi-User RAM Bus........................................................... 3-13

3.1.5 SDMA and Snooping................................................................................................. 3-13

3.1.6 Bus Selection Mechanisms ........................................................................................ 3-13

3.1.7 SDMA Internal Resource........................................................................................... 3-13

3.1.8 Programming Model of the Serial DMA ................................................................... 3-14

3.1.8.1 Serial DMA Status Register (SDSR) ..................................................................... 3-14

3.1.8.2 Serial DMA Mode Register (SDMR) .................................................................... 3-16

3.1.8.3 Serial DMA Threshold Registers (SDTR1 and SDTR2)....................................... 3-18

3.1.8.4 Serial DMA Hysteresis Registers (SDHY1 and SDHY2)..................................... 3-20

3.2 Interrupt Controller ........................................................................................................3-24

3.2.1 Interrupt Configuration .............................................................................................. 3-25

3.2.2 Interrupt Source Priorities.......................................................................................... 3-28

3.2.3 UCC Relative Priority................................................................................................ 3-33

3.2.4 Highest Priority Interrupt........................................................................................... 3-33

3.2.5 Masking Interrupt Sources......................................................................................... 3-33

3.2.6 Interrupt Vector Generation and Calculation............................................................. 3-34

3.3 Programming Model ...................................................................................................... 3-36