IC设计工程师必备checklist（英文版）
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2022-03-20
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ASIC-System on Chip-VLSI Design: ASIC Design Check List
https://asic-soc.blogspot.com/2007/10/asic-design-check-list.html
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ASIC Design Check List
Silicon Process and Library Characteristics
What exact process are you using?
How many layers can be used for this design?
Are the Cross talk Noise constraints, Xtalk Analysis configuration, Cell EM & Wire EM
available?
Design Characteristics
What is the design application?
Number of cells (placeable objects)?
Is the design Verilog or VHDL?
Is the netlist flat or hierarchical?
Is there RTL available?
Is there any datapath logic using special datapath tools?
Is the DFT to be considered?
Can scan chains be reordered?
Is memory BIST, boundary scan used on this design?
Are static timing analysis constraints available in SDC format?
Clock Characteristics
How many clock domains are in the design?
What are the clock frequencies?
Is there a target clock skew, latency or other clock requirements?
Does the design have a PLL?
If so, is it used to remove clock latency?
Is there any I/O cell in the feedback path?
Is the PLL used for frequency multipliers?
Are there derived clocks or complex clock generation circuitry?
Are there any gated clocks?
If yes, do they use simple gating elements?
Is the gate clock used for timing or power?
For gated clocks, can the gating elements be sized for timing?
Are you muxing in a test clock or using a JTAG clock?
Available cells for clock tree?
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