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PXI Hardware Specification 2.1
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PXI是根据仪表的需要,基于CompactPCI进行的扩展.可算做是cPCI的一个超集吧.
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Hardware Specification
PCI eXtensions for Instrumentation
An Implementation of
PXI Hardware Specification Rev. 2.1 02/04/2003
Revision 2.1
February 4, 2003
PXI Hardware Specification Rev. 2.1 02/04/2003 ii www.pxisa.org
IMPORTANT INFORMATION
Copyright
© Copyright 1997- 2003 PXI Systems Alliance. All rights reserved.
This document is copyrighted by the PXI Systems Alliance. Permission is granted to reproduce and distribute this
document in its entirety and without modification.
NOTICE
The PXI Hardware Specification is authored and copyrighted by the PXI Systems Alliance. The intent of the PXI
Systems Alliance is for the PXI Hardware Specification to be an open industry standard supported by a wide variety
of vendors and products. Vendors and users who are interested in developing PXI-compatible products or services, as
well as parties who are interested in working with the PXI Systems Alliance to further promote PXI as an open industry
standard are invited to contact the PXI Systems Alliance for further information.
The PXI Systems Alliance wants to receive your comments on this specification. Visit the PXI Systems Alliance web
site at
http://www.pxisa.org/
for contact information and to learn more about the PXI Systems Alliance.
The attention of adopters is directed to the possibility that compliance with or adoption of the PXI Systems Alliance
specifications may require use of an invention covered by patent rights. The PXI Systems Alliance shall not be
responsible for identifying patents for which a license may be required by any PXI Systems Alliance specification,
or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention.
PXI Systems Alliance specifications are prospective and advisory only. Prospective users are responsible for protecting
themselves against liability for infringement of patents.
The information contained in this document is subject to change without notice. The material in this document details
a PXI Systems Alliance specification in accordance with the license and notices set forth on this page. This document
does not represent a commitment to implement any portion of this specification in any company’s products.
The PXI Systems Alliance makes no warranty of any kind with regard to this material, including, but not limited to,
the implied warranties of merchantability and fitness for a particular purpose. The PXI Systems Alliance shall not be
liable for errors contained herein or for incidental or consequential damages in connection with the furnishing,
performance, or use of this material.
Compliance with this specification does not absolve manufacturers of PXI equipment from the requirements of safety
and regulatory agencies (UL, CSA, FCC, IEC, etc.).
Trademarks
PXI™ is a trademark of the PXI Systems Alliance.
PICMG™ and CompactPCI® are trademarks of the PCI Industrial Computation Manufacturers Group.
Product and company names are trademarks or trade names of their respective companies.
© PXI Systems Alliance iii PXI Hardware Specification Rev. 2.1 02/04/2003
PXI Specification Revision History
This section is an overview of the revision history of the PXI specification.
Revision 1.0, August 20, 1997
This is the first public revision of the PXI specification.
Revision 2.0, July 28, 2000
This revision incorporates changes that include but are not limited to the following:
• Transfer of the specification ownership to the PXI System Alliance.
• Modification of pin assignment to comply with PICMG 2.0 R3.0 that include addition of GA0-GA4 signals to all
slots, removal of PRST#, DEG#, and FAL# from peripheral slots, addition of IPMB bus to all slots, addition of
HEALTHY# to all slots, addition of SMB bus to system slot, addition of BD_SEL# to peripheral slots, changing
SYSEN# to UNC on peripheral slots, and changing IDSEL to GND on system slot.
• Removal of references to Serialized IRQ due to PICMG 2.0 R3.0 adoption.
• Addition of 66MHz PCI operation.
• Removal of J5 as a reserved connector.
• Allowance of J5 to be populated only in custom PXI boards and backplanes that are offered as a system.
• Allowance for star trigger routings other than only peripheral slots in first two segments in PXI backplanes with
more than two segments.
• Allowance for the local bus to be routed between segments.
• Addition of rules about connecting the IDSEL lines of first segment PCI devices, bridges, and peripheral slots to
AD[25:31] and routing peripheral slot INT lines to system slot INT lines based on the peripheral slot IDSEL to
AD[25:31] connection.
• Increased required current on 3.3V for a 5V backplane to comply with requirement of 3.3V being available
according to PICMG 2.0 R3.0
• Addition of Windows 98 and Windows 2000 software frameworks.
• Removal of requirements for PC 9X compliance for controllers and peripherals.
• Addition of segment divider glyph.
• Removal of SHALL NOT rule for chassis ground to digital ground connection and addition of SHOULD NOT
recommendation for chassis ground to digital ground.
• Modification of requirements for EMC that includes changing IEC 61326-1:1997 to IEC 61326?1:1998 and IEC
CISPR-11 to EN5501.
• Addition of maximum Voh and minimum Vol values for trigger bus.
• Modification of the legal notice.
• Addition of license requirement for use of the PXI logo.
Revision 2.1, February 4, 2003
This revision incorporates changes that include but are not limited to the following:
• Removal of software related rules (Refer to the now separate PXI Software Specification).
• Removal of J4 as a reserved connector.
• Addition of rules associated with 6U chassis that support stacking of two 3U modules in a single 6U slot.
• Addition of a rule that limits the maximum number of slots in a chassis to 31.
• Combining the chassis power supply minimum power requirements tables into one table and removing the
recommended current entries in favor of required current entries.
PXI Hardware Specification Rev. 2.1 02/04/2003 iv www.pxisa.org
• Increasing the -12V required current.
• Addition of the minimum current-handling requirement for each slot.
• Turning the recommendation that modules document their required current into a rule.
• Addition of a recommendation to limit the maximum power that a module dissipates within a chassis.
• Addition of a rule that requires filler panels to be installed in chassis slots that are not populated.
• Addition of an implementation note that recommends not mapping a module's registers mapped to PCI I/O Space.
• Modification of J2/P2 B19 and J2/P2 B21 pin assignments from GND to RSV on star trigger and peripheral
pinouts.
© PXI Systems Alliance v PXI Hardware Specification Rev. 2.1 02/04/2003
Contents
1. Introduction
1.1 Objectives........................................................................................................................................ 1
1.2 Intended Audience and Scope......................................................................................................... 2
1.3 Background and Terminology......................................................................................................... 2
1.4 Applicable Documents .................................................................................................................... 3
1.5 Useful Web Sites............................................................................................................................. 4
2. PXI Architecture Overview
2.1 Mechanical Architecture Overview ................................................................................................ 5
2.1.1 Chassis Supporting Stacking 3U Modules in a 6U Slot.................................................. 6
2.1.2 System Slot Location ...................................................................................................... 7
2.1.3 Additional Mechanical Features...................................................................................... 8
2.1.4 Interoperability with CompactPCI .................................................................................. 8
2.2 Electrical Architecture Overview.................................................................................................... 8
2.2.1 Peripheral Component Interconnect (PCI) Features ....................................................... 9
2.2.2 Local Bus......................................................................................................................... 9
2.2.3 System Reference Clock ................................................................................................. 10
2.2.4 Trigger Bus...................................................................................................................... 10
2.2.5 Star Trigger ..................................................................................................................... 10
2.2.6 System Expansion with PCI-PCI Bridge Technology .................................................... 11
2.3 Software Architecture Overview..................................................................................................... 11
3. Mechanical Requirements
3.1 CompactPCI Mechanical Requirements ......................................................................................... 12
3.2 Maximum Number of Slots............................................................................................................. 12
3.3 System Slot Location and Rules ..................................................................................................... 12
3.4 Logos and Compatibility Glyphs .................................................................................................... 13
3.5 Slot Numbering for 6U Chassis that Support 3U Stacking............................................................. 14
3.6 Environmental Testing.................................................................................................................... 15
3.7 Cooling Specifications .................................................................................................................... 16
3.7.1 Plug-in Module Requirements ........................................................................................ 16
3.7.2 Chassis Requirements ..................................................................................................... 16
3.8 Chassis and Module Grounding Requirements and EMI Guidelines ............................................. 17
3.9 Regulatory Requirements................................................................................................................ 17
3.9.1 Requirements for EMC ................................................................................................... 17
3.9.2 Requirements for Electrical Safety ................................................................................. 17
3.9.3 Additional Requirements for Chassis.............................................................................. 18
4. Electrical Requirements
4.1 PXI Signal Groups .......................................................................................................................... 19
4.1.1 P1/J1: Signals .................................................................................................................. 19
4.1.2 P2/J2: Signals .................................................................................................................. 19
4.1.2.1 Signals from CompactPCI 64-bit Connector Specification....................... 20
4.1.2.2 PXI Bused Reserved Signals ..................................................................... 21
4.1.2.3 Local Buses................................................................................................ 21
4.1.2.4 Reference Clock: PXI_CLK10.................................................................. 23
4.1.2.5 Trigger Bus ................................................................................................ 23
4.1.2.6 Star Trigger................................................................................................ 27
4.1.3 Electrical Guidelines for 6U............................................................................................ 29
4.1.3.1 6U Peripheral Module Connector Population............................................ 29
4.1.3.2 6U Chassis that Support Stacking 3U Modules......................................... 29
4.2 Connector Pin Assignments (J1/P1 and J2/P2)............................................................................... 30
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- chiclee2012-01-05完全没用 就是一个brief而已
pc_repair
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