16QAM的System Generator模型

function qammap_config(this_block) % Revision History: % % 19-May-2010 (14:48 hours): % Original code was machine generated by Xilinx's System Generator after parsing % C:\Users\Administrator\Desktop\QAM\qammap.v % % this_block.setTopLevelLanguage('Verilog'); this_block.setEntityName('qammap'); % System Generator has to assume that your entity has a combinational feed through; % if it doesn't, then comment out the following line: this_block.tagAsCombinational; this_block.addSimulinkInport('i'); this_block.addSimulinkInport('q'); this_block.addSimulinkInport('reset'); this_block.addSimulinkOutport('i_map'); this_block.addSimulinkOutport('q_map'); i_map_port = this_block.port('i_map'); i_map_port.setType('Fix_3_0'); q_map_port = this_block.port('q_map'); q_map_port.setType('Fix_3_0'); % ----------------------------- if (this_block.inputTypesKnown) % do input type checking, dynamic output type and generic setup in this code block. if (this_block.port('i').width ~= 2); this_block.setError('Input data type for port "i" must have width=2.'); end if (this_block.port('q').width ~= 2); this_block.setError('Input data type for port "q" must have width=2.'); end if (this_block.port('reset').width ~= 1); this_block.setError('Input data type for port "reset" must have width=1.'); end this_block.port('reset').useHDLVector(false); end % if(inputTypesKnown) % ----------------------------- % System Generator found no apparent clock signals in the HDL, assuming combinational logic. % ----------------------------- if (this_block.inputRatesKnown) inputRates = this_block.inputRates; uniqueInputRates = unique(inputRates); outputRate = uniqueInputRates(1); for i = 2:length(uniqueInputRates) if (uniqueInputRates(i) ~= Inf) outputRate = gcd(outputRate,uniqueInputRates(i)); end end % for(i) for i = 1:this_block.numSimulinkOutports this_block.outport(i).setRate(outputRate); end % for(i) end % if(inputRatesKnown) % ----------------------------- % (!) Set the inout port rate to be the same as the first input % rate. Change the following code if this is untrue. uniqueInputRates = unique(this_block.getInputRates); % Add addtional source files as needed. % |------------- % | Add files in the order in which they should be compiled. % | If two files "a.vhd" and "b.vhd" contain the entities % | entity_a and entity_b, and entity_a contains a % | component of type entity_b, the correct sequence of % | addFile() calls would be: % | this_block.addFile('b.vhd'); % | this_block.addFile('a.vhd'); % |------------- % this_block.addFile(''); % this_block.addFile(''); this_block.addFile('qammap.v'); return;