Contents
Chapter 1 Introduction
1
1
2
3
4
Hardware Description Languages
Th
e
Verilog Family of Languages
Mixed-Signa
l
Simulators
Application
s
of Verilog-AMS
4.1
4.2
4.3
4.4
4.5
Component Modeling
Test Benches
Simulation Acceleration
Mixed-Signal Design
Top-Down Design
Chapter 2 Top-Down Design
1
2
3
4
5
Mixed-Signal Design Productivity
Traditional Approaches to Mixed-Signal Design
2.1
2.2
Bottom-Up Design
Moving to Top-Down Design
Principles of Top-Down Design
3.1
3.2
3.3
3.4
3.5
A Shared Design Representation
Every Change is Verified
Verification Planning
Multiple Passes
Executable Specifications and Plans
A
Rigorous Top-Down Design Process
4.1
4.2
4.3
4.4
4.5
4.6
Simulation and Modeling Plans
System-Level Verification
Mixed-Level Simulation
Bottom-Up Verification
Final Verification
Test
Furthe
r
Benefits of Top-Down Design
5.1
5.2
5.3
5.4
5.5
Improves Communications Between Engineers
Improves Productivity
Improves Ability to Handle Complex Designs
Allows Parallel Execution of Design Tasks
Supports IP Reuse
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2
5
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8
10
10
11
11
13
13
16
1
7
17
19
20
21
22
23
23
24
24
26
27
28
29
30
3
0
30
3
0
3
1
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