xilinx开发实用教程光盘-徐文波田耘-第二版、资源-CSDN文库

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xilinx开发实用教程光盘-徐文波田耘-第二版、（2000个子文件）

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DS260 March 1, 2011 www.xilinx.com 1

Product Specification

United States and other countries. MATLAB is a registered trademark of The MathWorks, Inc. All other trademarks are the property of their respective owners.

Introduction

The Xilinx LogiCORE™ IP Fast Fourier Transform

(FFT) implements the Cooley-Tukey FFT algorithm, a

computationally efficient method for calculating the

Discrete Fourier Transform (DFT).

Features

• Drop-in module for Kintex™-7, Virtex

-7, Virtex®-6,

Virtex-5, Virtex-4, Spartan®-6, Spartan-3/XA,

Spartan-3E/XA and Spartan-3A/XA/AN/3A DSP

FPGAs

• Forward and inverse complex FFT, run-time

configurable

• Transform sizes N = 2

, m = 3 – 16

• Data sample precision b

= 8 – 34

• Phase factor precision b

= 8 – 34

• Arithmetic types:

¨ Unscaled (full-precision) fixed-point

¨ Scaled fixed-point

¨ Block floating-point

• Fixed-point or floating-point interface

• Rounding or truncation after the butterfly

• Block RAM or Distributed RAM for data and

phase-factor storage

• Optional run-time configurable transform point

size

• Run-time configurable scaling schedule for scaled

fixed-point cores

• Bit/digit reversed or natural output order

• Optional cyclic prefix insertion for digital

communications systems

• Four architectures offer a trade-off between core

size and transform time

• Bit-accurate C model and MEX function for system

modeling available for download

• For use with Xilinx CORE Generator™ software

and Xilinx System Generator for DSP v13.1

LogiCORE IP

Fast Fourier Transform v7.1

DS260 March 1, 2011 Product Specification

LogiCORE IP Facts Table

Core Specifics

Supported

Device Family

(1)

1. For a complete listing of supported devices, see the release notes

for this core.

Virtex-7 and Kintex-7,

Virtex-6, Virtex-5, Virtex-4,

Spartan-6, Spartan-3/XA, Spartan-3E/XA,

Spartan-3A/3AN/3A DSP/XA

Supported User

Interfaces

Not Applicable

Resources

(2)

2. Resources listed here are for Virtex-6 devices. For more complete

device performance numbers, see Table 7-Table 10.

Frequency

Configuration LUTs FFs

DSP

Slices

Block

RAMs

(3)

3. Based on 18K block RAMs.

Max.

Freq.

(4)

4. Performance numbers listed are for Virtex-6 FPGAs. For more

complete performance data, see Table 7-Table 10.

Radix-2,

2048-point,

variable point

size, 16-bit

data/phase

factors, scaled,

convergent

rounding

1092 1265 3 5 395 MHz

Provided with Core

Documentation

Product Specification

Design Files Netlist

Example Design Not Provided

Test Bench Not Provided

Constraints File Not Applicable

Simulation

Model

VHDL behavioral model in the xilinxcorelib library

VHDL UniSim structural model

Verilog UniSim structural model

Tested Design Tools

Design Entry

Tools

CORE Generator tool 13.1

System Generator for DSP 13.1

Simulation

Mentor Graphics ModelSim 6.6d

Cadence Incisive Enterprise Simulator (IES) 10.2

Synopsys VCS and VCS MX 2010.06

ISIM 13.1

Synthesis Tools N/A

Support

Provided by Xilinx, Inc.

DS260 March 1, 2011 www.xilinx.com 2

Product Specification

LogiCORE IP Fast Fourier Transform v7.1

Overview

The FFT core computes an N-point forward DFT or inverse DFT (IDFT) where N can be 2

, m = 3–16.

For fixed-point inputs, the input data is a vector of N complex values represented as dual b

-bit two’s-complement

numbers, that is, b

bits for each of the real and imaginary components of the data sample, where b

is in the range

8 to 34 bits inclusive. Similarly, the phase factors b

can be 8 to 34 bits wide.

For single-precision floating-point inputs, the input data is a vector of N complex values represented as dual 32-bit

floating-point numbers with the phase factors represented as 24- or 25-bit fixed-point numbers.

All memory is on-chip using either block RAM or distributed RAM. The N element output vector is represented

using b

bits for each of the real and imaginary components of the output data. Input data is presented in natural

order and the output data can be in either natural or bit/digit reversed order. The complex nature of data input and

output is intrinsic to the FFT algorithm, not the implementation.

Three arithmetic options are available for computing the FFT:

• Full-precision unscaled arithmetic

• Scaled fixed-point, where the user provides the scaling schedule

• Block floating-point (run-time adjusted scaling)

The point size N, the choice of forward or inverse transform, the scaling schedule and the cyclic prefix length are

run-time configurable. Transform type (forward or inverse), scaling schedule and cyclic prefix length can be

changed on a frame-by-frame basis. Changing the point size resets the core.

Four architecture options are available: Pipelined, Streaming I/O, Radix-4, Burst I/O, Radix-2, Burst I/O, and

Radix-2 Lite, Burst I/O. For detailed information about each architecture, see "Architecture Options."

Theory of Operation

The FFT is a computationally efficient algorithm for computing a Discrete Fourier Transform (DFT) of sample sizes

that are a positive integer power of 2. The DFT of a sequence is defined as

Equation 1

where N is the transform size and . The inverse DFT (IDFT) is given by

Equation 2

Algorithm

The FFT core uses the Radix-4 and Radix-2 decompositions for computing the DFT. For Burst I/O architectures, the

decimation-in-time (DIT) method is used, while the decimation-in-frequency (DIF) method is used for the Pipe-

lined, Streaming I/O architecture. When using Radix-4 decomposition, the N-point FFT consists of log

(N) stages,

with each stage containing N/4 Radix-4 butterflies. Point sizes that are not a power of 4 need an extra Radix-2 stage

for combining data. An N-point FFT using Radix-2 decomposition has log

(N) stages, with each stage containing

N/2 Radix-2 butterflies.

The inverse FFT (IFFT) is computed by conjugating the phase factors of the corresponding forward FFT.

(), 0, , 1Xk k N=−K

(), 0, , 1xn n N=−K

() () 0, , 1

jnk N

Xk xne k N

−

==−

∑

1j =−

() () 0, , 1

jnk N

xn Xke n N

−

==−

∑

DS260 March 1, 2011 www.xilinx.com 3

Product Specification

LogiCORE IP Fast Fourier Transform v7.1

Finite Word Length Considerations

The Burst I/O architectures process an array of data by successive passes over the input data array. On each pass,

the algorithm performs Radix-4 or Radix-2 butterflies, where each butterfly picks up four or two complex numbers,

respectively, and returns four or two complex numbers to the same memory. The numbers returned to memory by

the core are potentially larger than the numbers picked up from memory. A strategy must be employed to accom-

modate this dynamic range expansion. A full explanation of scaling strategies and their implications is beyond the

scope of this document; for more information about this topic; see [Ref 1] and [Ref 2].

For a Radix-4 DIT FFT, the values computed in a butterfly stage can experience growth by a factor of up to

. This implies a bit growth of up to 3 bits.

For Radix-2, the growth is by a factor of up to . This implies a bit growth of up to 2 bits. This bit

growth can be handled in three ways:

• Performing the calculations with no scaling and carrying all significant integer bits to the end of the

computation

• Scaling at each stage using a fixed-scaling schedule

• Scaling automatically using block floating-point

All significant integer bits are retained when using full-precision unscaled arithmetic. The width of the data path

increases to accommodate the bit growth through the butterfly. The growth of the fractional bits created from the

multiplication are truncated (or rounded) after the multiplication. The width of the output is (input width +

log

(transform length) + 1). This accommodates the worst case scenario for bit growth.

Consider an unscaled Radix-2 DIT FFT: the data path in each stage must grow by 1 bit as the adder and subtractor

in the butterfly may add/subtract two full-scale values and produce a sample which has grown in width by 1 bit.

This yields the log

(transform length) part of the increase in the output width relative to the input width. The com-

plex multiplier preserves the magnitude of an input (as it applies a rotation on the complex plane), but can theoret-

ically produce bit-growth when the magnitude of the input is greater than 1 (for example, 1+j has a magnitude of

1.414). This means that the complex multiplier bit growth must only be considered once in the entire FFT process,

yielding the additional +1 increase in the output width relative to the input width. For example, a 1024-point trans-

form with an input of 16 bits consisting of 1 integer bit and 15 fractional bits has an output of 27 bits with 12 integer

bits and 15 fractional bits. Note that the core does not have a specific location for the binary point. The output sim-

ply maintains the same binary point location as the input. For the preceding example, a 16 bit input with 3 integer

bits and 13 fractional bits would have an unscaled output of 27 bits with 14 integer bits and 13 fractional bits.

When using scaling, a scaling schedule is used to divide by a factor of 1, 2, 4, or 8 in each stage. If scaling is insuffi-

cient, a butterfly output may grow beyond the dynamic range and cause an overflow. As a result of the scaling

applied in the FFT implementation, the transform computed is a scaled transform. The scale factor s is defined as

Equation 3

where b

is the scaling (specified in bits) applied in stage i.

The scaling results in the final output sequence being modified by the factor 1/s. For the forward FFT, the output

sequence X’ (k), k = 0,...,N - 1 computed by the core is defined as

Equation 4

132 5.242≈+

122.414+≈

log 1

−

∑

'2/

() () () 0, , 1

jnk N

Xk Xk xne k N

−

== =−

∑

DS260 March 1, 2011 www.xilinx.com 4

Product Specification

LogiCORE IP Fast Fourier Transform v7.1

For the inverse FFT, the output sequence is

Equation 5

If a Radix-4 algorithm scales by a factor of 4 in each stage, the factor of 1/s is equal to the factor of 1/N in the inverse

FFT equation (Equation 2). For Radix-2, scaling by a factor of 2 in each stage provides the factor of 1/N.

With block floating-point, each stage applies sufficient scaling to keep numbers in range, and the scaling is tracked

by a block exponent.

As with unscaled arithmetic, for scaled and block floating-point arithmetic, the core does not have a specific loca-

tion for the binary point. The location of the binary point in the output data is inherited from the input data and

then shifted by the scaling applied.

Floating-Point Considerations

The FFT core optionally accepts data in IEEE-754 single-precision format with 32-bit words consisting of a 1-bit

sign, 8-bit exponent, and 23-bit fraction. The construction of the word matches that of the

Xilinx Floating-Point Operator core.

Implementing full floating-point on an FPGA can be expensive in terms of the resources required. The float-

ing-point option in the Xilinx FFT core utilizes a higher precision fixed-point FFT internally to achieve similar noise

performance to a full floating-point FFT, with significantly fewer resources. Figure 1 illustrates the two levels of

noise performance possible by selecting either 24 bits or 25 bits for the phase factor width. By increasing the phase

factor width to 25 bits, more resources may be required, depending on the target FPGA device.

X-Ref Target - Figure 1

Figure 1: Comparison of Two Levels of Noise Performance

() () 0, , 1

jnk N

xn X ke n N

−

==−

∑

DS260 March 1, 2011 www.xilinx.com 5

Product Specification

LogiCORE IP Fast Fourier Transform v7.1

Figure 1 shows the ratio of the RMS difference between various models and the double-precision MATLAB® FFT to

the data set peak amplitude. The models shown are the single-precision MATLAB FFT function (calculated by

casting the input data to single-precision floating-point type), the Xilinx FFT core using a 24-bit phase factor width,

and the Xilinx FFT core using a 25-bit phase factor width. To calculate the error signal, a randomized impulse (in

magnitude and time) was used as the input signal, with the RMS error averaged over five simulation runs.

All optimization options (memory types and XtremeDSP™ slice optimization) remain available when float-

ing-point input data is selected, allowing the user to trade off resources with transform time.

Transform time for Burst I/O architectures is increased by approximately N, the number of points in the transform,

due to the input normalization requirements. For the Pipelined, Streaming I/O architecture, the initial latency to fill

the pipeline is increased, but data still streams through the core with no gaps.

Denormalized Numbers

The floating-point interface to the FFT core does not support denormalized numbers. To match the behavior of the

Xilinx Floating-Point Operator core, the core treats denormalized operands as zero, with a sign taken from the

denormalized number.

NaNs and ± Infinity

If the core detects a NaN or ± Infinity value on the input, all output samples associated with the current input frame

are set to NaN. The sign bit is set to zero and all exponent and fraction bits are set to 1.

Real-Valued Input Data

The FFT core accepts complex data samples, but can perform a transform on real-valued data by setting all imagi-

nary input samples to zero.

Due to the finite wordlength effects described previously, noise is introduced during the transform, resulting in the

output data not being perfectly symmetric. The DIT and DIF FFT algorithms have different noise effects due to the

different calculation order.

For a thorough treatment of this topic, see [Ref 3] and [Ref 4].

The asymmetry between the two halves of the result is more noticeable at larger point sizes. In addition, the noise

is more prominent in the lower frequency bins. Therefore, Xilinx recommends that the upper half (N/2+1 to N

points) of the output data is used when performing a real-valued FFT.

Rounding Implementation

An option is available, in all architectures, to apply convergent rounding to the data after the butterfly stage. How-

ever, selecting this option does not apply convergent rounding to all points in the data path where wordlength

reduction occurs.

In particular, the outputs of all complex multipliers in the FFT data path are truncated to reduce data path width

(while still maintaining adequate precision) and a simple rounding constant added to the fractional bits. This con-

stant implements non-symmetric, round-towards-minus-infinity rounding, and can introduce a small bias to the

FFT results over a large number of samples.

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Wanderer001

2017-10-16

多谢。。。。。。。。。。。。
lwr052

2017-08-01

多谢，买了一本书，光盘不见了。

zhangg_chuan

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