USER'S MANUAL
S5PC100
June, 2009
REV 1.01
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S5PC100 RISC Microprocessor
User’s Manual, Revision 1.01
Publication Number:
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S5PC100_UM_REV1.0 iii
Revision History
Revision No. Description Author(s) Date
0.00 Initial Draft (Preliminary spec) AP design November, 2008
0.10
Following chapters are added
- Electrical Data, Mechanical Data
Following chapters are updated
- Overview, Memory map, Chip ID, GPIO, Clock
controller, Power management, Booting sequence,
DRAM controller, SROM controller, OneNAND
controller, NAND Flash controller, DMA controller,
System timer, MIPI DSIM, MIPI CSIS, USB HOST
controller, USB2.0 HS OTG, Modem interface,
SD/MMC controller, Display controller, Camera
interface, JPEG, FIMG-3DSE, TV & Video DAC,
Video Processor, Mixer, HDMI, Multi format codec,
Audio sub system, ADC & Touch screen interface,
Keypad interface, Security system, Advanced
crypto engine
AP design January, 2009
0.20
Unused pin are renamed.
AP Evaluation February, 2009
1.00
Public draft
AP Evaluation May, 2009
1.01
Some chapters are updated
AP Evaluation June, 2009
S5PC100 USER’S MANUAL (REV1.0) PRODUCT OVERVIEW
1.1-1
1.1 PRODUCT OVERVIEW
1 ARCHITECTURAL OVERVIEW
S5PC100 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones
and general applications, and integrates an ARM CortexTM-A8 which implements the ARM architecture V7-A with
supporting numerous peripherals.
To provide optimized Hardware (H/W) performance for the 3G and 3.5G communication services, S5PC100
adopts 64-bit internal bus architecture and includes many powerful hardware accelerators for tasks such as
motion video processing, display control and scaling. Integrated Multi Format Codec (MFC) supports encoding
and decoding of MPEG-1/2/4, H.263, H.264 and decoding of VC1, Divx. This Hardware accelerators support real-
time video conferencing and Analog TV out, HDMI for NTSC and PAL mode
The S5PC100 has an optimized interface to external memory capable of sustaining the demanding memory
bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory
ports for parallel access and DRAM port for high bandwidth. DRAM port can be configured to support mobile
DDR, DDR2 or LPDDR2.
Flash/ROM Port supports NAND Flash, NOR-Flash, OneNAND and ROM type external memory.
To reduce total system cost and enhance overall functionality, S5PC100 includes many hardware peripherals
such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2 and HSI, System Manager for
power management, CF+, ATA I/F, 4-channel UART, 24-channel DMA, 4-channel Timers, General I/O Ports, 3-ch
IIS, 1-ch S/PDIF, 2-ch CAN bus, IIC-BUS interface, 3-ch HS-SPI, USB Host v1.1, USB OTG v2.0 operating at
high speed (480Mbps), SD Host & High Speed Multi-Media Card Interface and PLLs for clock generation.
Package on Package (POP) option with MCP is available for small form factor applications.
Salient features of S5PC100 are summarized below:
PRODUCT OVERVIEW S5PC100 USER’S MANUAL (REV1.0)
1.1-2
2 BLOCK DIAGRAM
This section summarizes the features of the S5PC100. Figure 1.1- 1 shows an overall block diagram of the
S5PC100.
ARM CoreSystem Peripheral
Connectivity
Multimedia
Acceleration
x64 Multi-Layer AHB/AXI Bus
Memory Subsystem
Power
Management
TFT LCD
Controller / DSI
RTC
PLL x 4
Timer / PWM
Watch Dog Timer
DMA(24ch)
Keypad (8 x 8)
ADC & Touch Screen
I2S (3ch)
AC97/PCM I/F(2ch)
S/PDIF (1ch)
UART (4ch)
IrDA v1.1
I2C(2ch)
HS-SPI (3ch)
MIPI-HSI/Modem I/F
USB Host 1.1 & OTG 2.0
CAN I/F (2ch)
HS-MMC/SD (3ch)
CFII(ATA)
GPIO
32KB/32KB I/D Cache
667MHz @ 1.20 V
256KB
L2 Cache
NEON
Secure
iRAM
Secure
iROM
Crypto
Accelerator
Dynamic Voltage
Frequency Scaling
24/18-bit TFT LCD
8-bit for Dual i80
1024x768 output
5-layer PIP
16-bit a-blending
Camera IF / CSI-2
720p 30fps MFC
Codec - H.263/H.264/MPEG4
Decoder - MPEG2/VC-1/Divx
LCDC/OSD
3D Graphics Engine
2D Graphics Engine
NTSC, PAL TV out
(MIPI DSI/HDMI)
JPEG CODEC
SRAM/ROM/NOR
OneNAND
mDDR / DDR2 /
mDDR2
NAND Flash
OneDRAM
CortexA8
Figure 1.1- 1 S5PC100 Block Diagram
