基于波形发生器的部分代码
module dds (sys_clk, sys_rst_n, fword, pword, da_clk, rom_addr);
input sys_clk; //系统时钟
input sys_rst_n; //系统复位，低电平有效
input[31:0]fword; //输入频率字
input[11:0]pword; //输入相位字
output[11:0]rom_addr;
output da_clk; //D/A 时钟
reg[31:0]fword_r;
reg[11:0]pword_r;
reg[31:0]freq_count;
reg[11:0]rom_addr;
/*******************************************************************************************************
** Main Program
**
********************************************************************************************************/
assign da_clk = sys_clk;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0) begin
fword_r <= 32'h0000;
end
else
fword_r <= fword;
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0) begin
pword_r <= 12'h0000;
end
else
pword_r <= pword;
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0) begin
freq_count <= 32'h0000;
end
else
freq_count <= freq_count + fword_r; //频率控制器
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0) begin
rom_addr <= 32'h0000;
end
else
rom_addr <= freq_count[31:20] + pword_r; //相位控制器
end
endmodule
