Instructor Guide
Course materials may not be reproduced in whole or in part
without the prior written permission of IBM.
1-20 AIX 5L System Administration III © Copyright IBM Corp. 2000, 2006
Caches
To minimize the number of times the program has to experience the RAM latency,
systems incorporate caches for instructions and data. If the required instruction or data
is already in the cache (a cache hit), it is available to the processor on the next cycle
(that is, no delay occurs); otherwise, a cache miss occurs. If a given access is both a
TLB miss and a cache miss, both delays occur consecutively.
Depending on the hardware architecture, there are two or three levels of cache, usually
called L1, L2, and L3. If a particular storage reference results in an L1 miss, then L2 is
checked. If L2 generates a miss, then the reference goes to the next level, either L3, if it
is present, or RAM.
Pipeline and registers
A pipelined, superscalar architecture allows for the simultaneous processing of multiple
instructions, under certain circumstances. Large sets of general-purpose registers and
floating-point registers make it possible to keep considerable amounts of the program's
data in registers, rather than continually storing and reloading the data.
Operating system hierarchy overview
The operating system works on a thread level. When a user requests the execution of a
program, AIX performs a number of operations to transform the executable program on
disk to a running program. First, the directories in the user's current PATH must be
scanned to find the correct copy of the program. Then the system loader (not to be
confused with ld, the binder) must resolve any external references from the program to
shared libraries. Finally, the system branches to the entry point of the program and the
resulting page fault causes the program page that contains the entry point to be brought
into RAM.
Interrupt handlers
The mechanism for notifying the operating system that an external event has taken
place is to interrupt the currently running thread and transfer control to an interrupt
handler (FLIH or SLIH). Before the interrupt handler can run, enough of the
general-purpose registers must be saved to ensure that the system can restore the
context of the running thread after interrupt handling is complete.
Threads
A thread is the current execution state of a single instance of a program. In AIX, access
to the processor and other resources is allocated on a thread basis, rather than a
process basis. Multiple threads can be created within a process by the application
program. Those threads share the resources owned by the process within which they
are running.
