FM25CL64B-GTR_2017-11-10.PDF资源-CSDN文库

需积分: 10 100 浏览量 2021-05-14 17:03:08 上传评论收藏 739KB PDF 举报

本文档介绍的是 Cypress Semiconductor Corporation 生产的 FM25CL64B-GTR，这是一款基于 Ferroelectric Random Access Memory (F-RAM) 技术的串行（SPI）存储器，具有64-Kbit（8K × 8）的存储容量。F-RAM 是一种非易失性内存，它结合了RAM的高速读写操作和闪存的非易失性特性。该芯片的主要特点包括： 1. 高耐久性：FM25CL64B支持100万亿次（1014）的读/写操作，远超传统的闪存和EEPROM，确保了极高的耐用性。 2. 数据保留时间长：该芯片能提供151年的数据保留时间，保证了长时间的数据稳定性。 3. 无延迟写入：采用NoDelay™技术，写入操作在总线速度下完成，无需等待，一旦数据成功传输到设备，就会立即写入内存阵列，提高了系统的效率。 4. 快速SPI接口：支持高达20MHz的频率，可以作为串行闪存和EEPROM的直接硬件替代品，兼容SPI模式0 (0, 0) 和模式3 (1, 1)。 5. 写保护机制：硬件保护通过Write Protect (WP)引脚实现，软件保护则通过Write Disable指令实现，同时支持对内存区域进行1/4、1/2或整个数组的块保护。 6. 低功耗：在1MHz工作时，主动电流仅为200μA；待机状态下，电流典型值为3μA，显著降低了系统能耗。 7. 低电压运行：工作电压范围为2.7V至3.65V，适应性强。 8. 工业级温度范围：能够在-40°C至+85°C的环境中稳定工作。 9. 封装选项：提供8引脚的小外形集成电路（SOIC）封装和8引脚的薄型双平无引脚（DFN）封装，满足不同设计需求。 10. RoHS合规：符合欧盟关于限制有害物质的规定，有利于环保。功能描述中提到，FM25CL64B利用先进的铁电工艺制造，它是一种非易失性内存，读写操作与RAM类似，但提供了更可靠的数据保留时间，并消除了串行闪存、EEPROM等其他非易失性存储器带来的复杂性、额外开销和系统级可靠性问题。与传统串行闪存和EEPROM不同，FM25CL64B的写操作不需延迟，数据在传输完成后即刻写入，提高了系统的响应速度和效率。此外，其出色的写耐久性也是相对于其他非易失性存储器的一大优势。

资源推荐

资源详情

资源评论

FM25CL64B

64-Kbit (8K × 8) Serial (SPI) F-RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-84477 Rev. *I Revised April 20, 2017

64-Kbit (8K × 8) Serial (SPI) F-RA M

Features

■ 64-Kbit ferroelectric random access memory (F-RAM) logically

organized as 8K × 8

❐ High-endurance 100 trillion (10

) read/writes

❐ 151-year data retention (See the Data Retention and

Endurance table)

❐ NoDelay™ writes

❐ Advanced high-reliability ferroelectric process

■ Very fast serial peripheral interface (SPI)

❐ Up to 20 MHz frequency

❐ Direct hardware replacement for serial flash and EEPROM

❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)

■ Sophisticated write protection scheme

❐ Hardware protection using the Write Protect (WP) pin

❐ Software protection using Write Disable instruction

❐ Software block protection for 1/4, 1/2, or entire array

■ Low power consumption

❐ 200 A active current at 1 MHz

❐ 3 A (typ) standby current

■ Low-voltage operation: V

= 2.7 V to 3.65 V

■ Industrial temperature: –40 C to +85 C

■ Packages

❐ 8-pin small outline integrated circuit (SOIC) package

❐ 8-pin thin dual flat no leads (DFN) package

■ Restriction of hazardous substances (RoHS) compliant

Functional Description

The FM25CL64B is a 64-Kbit nonvolatile memory employing an

advanced ferroelectric process. A ferroelectric random access

memory or F-RAM is nonvolatile and performs reads and writes

similar to a RAM. It provides reliable data retention for 151 years

while eliminating the complexities, overhead, and system level

reliability problems caused by serial flash, EEPROM, and other

nonvolatile memories.

Unlike serial flash and EEPROM, the FM25CL64B performs

write operations at bus speed. No write delays are incurred. Data

is written to the memory array immediately after each byte is

successfully transferred to the device. The next bus cycle can

commence without the need for data polling. In addition, the

product offers substantial write endurance compared with other

nonvolatile memories. The FM25CL64B is capable of supporting

read/write cycles, or 100 million times more write cycles

than EEPROM.

These capabilities make the FM25CL64B ideal for nonvolatile

memory applications requiring frequent or rapid writes.

Examples range from data collection, where the number of write

cycles may be critical, to demanding industrial controls where the

long write time of serial flash or EEPROM can cause data loss.

The FM25CL64B provides substantial benefits to users of serial

EEPROM or flash as a hardware drop-in replacement. The

FM25CL64B uses the high-speed SPI bus, which enhances the

high-speed write capability of F-RAM technology. The device

specifications are guaranteed over an industrial temperature

range of –40 C to +85 C.

For a complete list of related documentation, click here.

Instruction Decoder

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

8 K x 8

F-RAM Array

Data I/ O Register

Nonvolatile Status

HOLD

SCK

SOSI

Logic Block Diagram

FM25CL64B

Document Number: 001-84477 Rev. *I Page 2 of 21

Contents

Pinouts ..............................................................................3

Pin Definitions ..................................................................3

Functional Overview ........................................................4

Memory Architecture ........................................................4

Serial Peripheral Interface – SPI Bus ..............................4

SPI Overview ...............................................................4

SPI Modes ...................................................................5

Power Up to First Access ............................................6

Command Structure ....................................................6

WREN - Set Write Enable Latch .................................6

WRDI - Reset Write Enable Latch ...............................6

Status Register and Write Protection .............................6

RDSR - Read Status Register .....................................7

WRSR - Write Status Register ....................................7

Memory Operation ............................................................8

Write Operation ...........................................................8

Read Operation ...........................................................8

HOLD Pin Operation ...................................................9

Endurance .................................................................10

Maximum Ratings ...........................................................11

Operating Range .............................................................11

DC Electrical Characteristics ........................................11

Data Retention and Endurance .....................................12

Capacitance ....................................................................12

Thermal Resistance ........................................................12

AC Test Conditions ........................................................12

AC Switching Characteristics .......................................13

Power Cycle Timing .......................................................15

Ordering Information ......................................................16

Ordering Code Definitions .........................................16

Package Diagrams ..........................................................17

Acronyms ........................................................................19

Document Conventions .................................................19

Units of Measure .......................................................19

Document History Page .................................................20

Sales, Solutions, and Legal Information ......................21

Worldwide Sales and Design Support ....................... 21

Products ....................................................................21

PSoC® Solutions ......................................................21

Cypress Developer Community .................................21

Technical Support .....................................................21

FM25CL64B

Document Number: 001-84477 Rev. *I Page 3 of 21

Pinouts

Figure 1. 8-pin SOIC pinout

Figure 2. 8-pin DFN pinout

HOLD

SCK

Top View

not to scale

SCK

HOLD

PAD

EXPOSED

Top View

not to scale

Pin Definitions

Pin Name I/O Type Description

Input Chip Select. This active LOW input activates the device. When HIGH, the device enters

low-power standby mode, ignores other inputs, and tristates the output. When LOW, the device

internally activates the SCK signal. A falling edge on CS

must occur before every opcode.

SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising

edge and outputs occur on the falling edge. Because the device is synchronous, the clock

frequency may be any value between 0 and 20 MHz and may be interrupted at any time.

[1]

Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of

SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD

specifications.

[1]

Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all

other times including when HOLD

is LOW. Data transitions are driven on the falling edge of the

serial clock.

Input Write Protect. This active LOW pin prevents write operation to the Status Register when WPEN

is set to ‘1’. This is critical because other write protection features are controlled through the

Status Register. A complete explanation of write protection is provided in Status Register and

Write Protection on page 7. This pin must be tied to V

if not used.

HOLD

Input HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for

another task. When HOLD

is LOW, the current operation is suspended. The device ignores any

transition on SCK or CS

. All transitions on HOLD must occur while SCK is LOW. This pin must

be tied to V

if not used.

Power supply Ground for the device. Must be connected to the ground of the system.

Power supply Power supply input to the device.

EXPOSED PAD No connect The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. The

EXPOSED PAD should not be soldered on the PCB.

Note

1. SI may be connected to SO for a single pin data interface

FM25CL64B

Document Number: 001-84477 Rev. *I Page 4 of 21

Functional Overview

The FM25CL64B is a serial F-RAM memory. The memory array

is logically organized as 8,192 × 8 bits and is accessed using an

industry standard serial peripheral interface (SPI) bus. The

functional operation of the F-RAM is similar to serial flash and

serial EEPROMs. The major difference between the

FM25CL64B and a serial flash or EEPROM with the same pinout

is the F-RAM's superior write performance, high endurance, and

low power consumption.

Memory Architecture

When accessing the FM25CL64B, the user addresses 8K

locations of eight data bits each. These eight data bits are shifted

in or out serially. The addresses are accessed using the SPI

protocol, which includes a chip select (to permit multiple devices

on the bus), an opcode, and a two-byte address. The upper 3 bits

of the address range are ‘don’t care’ values. The complete

address of 13 bits specifies each byte address uniquely.

Most functions of the FM25CL64B are either controlled by the

SPI interface or handled by on-board circuitry. The access time

for the memory operation is essentially zero, beyond the time

needed for the serial protocol. That is, the memory is read or

written at the speed of the SPI bus. Unlike a serial flash or

EEPROM, it is not necessary to poll the device for a ready

condition because writes occur at bus speed. By the time a new

bus transaction can be shifted into the device, a write operation

is complete. This is explained in more detail in the interface

section.

Note The FM25CL64B contains no power management circuits

other than a simple internal power-on reset circuit. It is the user's

responsibility to ensure that V

is within datasheet tolerances

to prevent incorrect operation. It is recommended that the part is

not powered down with chip enable active.

Serial Peripheral Interface – SPI Bus

The FM25CL64B is a SPI slave device and operates at speeds

up to 20 MHz. This high-speed serial bus provides

high-performance serial communication to a SPI master. Many

common microcontrollers have hardware SPI ports allowing a

direct interface. It is quite simple to emulate the port using

ordinary port pins for microcontrollers that do not. The

FM25CL64B operates in SPI Mode 0 and 3.

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input

(SI), Serial Output (SO), and Serial Clock (SCK) pins.

The SPI is a synchronous serial interface, which uses clock and

data pins for memory access and supports multiple devices on

the data bus. A device on the SPI bus is activated using the CS

pin.

The relationship between chip select, clock, and data is dictated

by the SPI mode. This device supports SPI modes 0 and 3. In

both of these modes, data is clocked into the F-RAM on the rising

edge of SCK starting from the first rising edge after CS

goes

active.

The SPI protocol is controlled by opcodes. These opcodes

specify the commands from the bus master to the slave device.

After CS

is activated, the first byte transferred from the bus

master is the opcode. Following the opcode, any addresses and

data are then transferred. The CS

must go inactive after an

operation is complete and before a new opcode can be issued.

The commonly used terms in the SPI protocol are as follows:

SPI Master

The SPI master device controls the operations on a SPI bus. An

SPI bus may have only one master with one or more slave

devices. All the slaves share the same SPI bus lines and the

master may select any of the slave devices using the CS

pin. All

of the operations must be initiated by the master activating a

slave device by pulling the CS

pin of the slave LOW. The master

also generates the SCK and all the data transmission on SI and

SO lines are synchronized with this clock.

SPI Slave

The SPI slave device is activated by the master through the Chip

Select line. A slave device gets the SCK as an input from the SPI

master and all the communication is synchronized with this

clock. An SPI slave never initiates a communication on the SPI

bus and acts only on the instruction from the master.

The FM25CL64B operates as an SPI slave and may share the

SPI bus with other SPI slave devices.

Chip Select (CS

)

To select any slave device, the master needs to pull down the

corresponding CS pin. Any instruction can be issued to a slave

device only while the CS pin is LOW. When the device is not

selected, data through the SI pin is ignored and the serial output

pin (SO) remains in a high-impedance state.

Note A new instruction must begin with the falling edge of CS

Therefore, only one opcode can be issued for each active Chip

Select cycle.

Serial Clock (SCK)

The Serial Clock is generated by the SPI master and the

communication is synchronized with this clock after CS

goes

LOW.

The FM25CL64B enables SPI modes 0 and 3 for data

communication. In both of these modes, the inputs are latched

by the slave device on the rising edge of SCK and outputs are

issued on the falling edge. Therefore, the first rising edge of SCK

signifies the arrival of the first bit (MSB) of a SPI instruction on

the SI pin. Further, all data inputs and outputs are synchronized

with SCK.

Data Transmission (SI/SO)

The SPI data bus consists of two lines, SI and SO, for serial data

communication. SI is also referred to as Master Out Slave In

(MOSI) and SO is referred to as Master In Slave Out (MISO). The

master issues instructions to the slave through the SI pin, while

不需要忙检测

剩余20页未读，继续阅读

评论收藏

内容反馈

静默不言

粉丝: 116
资源: 45

FM25CL64B-GTR_2017-11-10.PDF

FM收音机资料.docx

三星CL系列规格书.pdf

FM24CL64B-GTR、MB85RS64驱动代码

FM25CL64.rar_ FM25CL64_FM25CL64 linux_FM25CL64 stm32_fm25cl64_li

STM32F103单片机_SPI读写FM25CL64铁电存储器驱动程序代码.zip

FM25CL64.rar_FM25CL64 stm32_STM32 HAL SPI FM25_fm25cl64 smt32_sp

STM32 FM25CL64B 铁电存储器

fm_vL-2016.03-SP1_linux64.spf

FM25L04B-G_fm25040b_

FM25CL64.zip_FM spi_FM25CL64 stm32_fm25cl64 spi_spi 铁电存储器_stm32

fm2018-380_cellphone_ref_v1.0.pdf

铁电存储器-FM25V10-GTR数据手册

mb_bios_ga-b85m-d3v_v2.x_fm.zip

FM25CL64.rar_FM25CL64 stm32_anyone8lf_fm25cl64_pasto8y_spi2

1768_FM25V10_SPI.rar_FM25V10.C_LPC1768 SSP_fm25v10代码_lpc1768 spi

STM32103RBT6单片机 SPI读写FM25CL64铁电存储器程序驱动源码.rar

最强大的软件无线电接收软件SDR-Radio V3_64-bit 2018-09-11_1011

fm2018手册集

SPI接口FM25CL64铁电存储器测试读写代码

铁电存储器FM25CL64的C51编程

STM32F103RCT6读写FM25CL64（已在工程中应用）

pyfm-2016.2.10-cp36-cp36m-win_amd64.whl.zip

FM2018-380_parameter tuning guide_v1.0

S7-300_FM350-1_Getting_Start.zip

问个芯-FM8035-58_1710494759.pdf

松下vp-8177调制信号发生器说明书national_vp-8177a_fm-am_signal_generator.pdf

stm32 模拟读写 铁电fm25cl64

DSP28335 FM25CL64

yaesu_ftm-10r_sm.pdf

最新资源

stm32 模拟读写铁电fm25cl64