About CPU
Where does the CPU core run when it starts up?
◦ 0xFFFFFFFC
◦ -> what’s the content of the address 0xFFFFFFFC?
How does the CPU core access the different IP blocks?
◦ LAW (Local Access Window): associate a range of 36-bit address space with a
particular target interface.
0x0000_0000 0x7fff_ffff DDR 2G Cacheable
0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
◦ CCSRBAR – define a window used to access all memory-mapped CCSR
0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
◦ SRAM window – define a window used to access the SRAM configured by L2 Cache
Must disable the Multiple-bit/Single-bit ECC error
Does the core use physical address or effective address to access the
IP blocks?
◦ Physical address
How does the effective address translate to physical address?
◦ TLB (Translation Lookaside buffer)
◦ TLB 0 and TLB1
What’s the difference?
How does the Linux kernel or U-Boot use them?
What’s the relationship between TLB and Linux kernel page table?
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