ARM DDI 0317A Copyright © 2006 ARM Limited. All rights reserved. v
List of Tables
CoreSight TPIU-Lite Technical Reference
Manual
Change History ............................................................................................................. ii
Table 2-1 Example port configurations ...................................................................................... 2-3
Table 2-2 Synchronous trace port pin encoding ........................................................................ 2-4
Table 2-3 Synchronous pin protocol .......................................................................................... 2-5
Table 3-1 TPIU programmable registers ................................................................................... 3-3
Table 3-2 Formatter and Flush Status Register bit assignments .............................................. 3-6
Table 3-3 Formatter and Flush Control Register bit assignments ............................................. 3-7
Table 3-4 Formatter Synchronization Counter Register bit assignments .................................. 3-9
Table 3-5 Integration Test Trigger In and Flush In Acknowledge Register bit assignments ... 3-10
Table 3-6 Integration Test Trigger In and Flush In Register bit assignments .......................... 3-11
Table 3-7 Integration Test ATB Data Register 0 bit assignments ........................................... 3-12
Table 3-8 Integration Test ATB Control Register 2 bit assignments ....................................... 3-12
Table 3-9 Integration Test ATB Control Register 0 bit assignments ....................................... 3-13
Table 3-10 Integration Mode Control Register bit assignments ................................................ 3-14
Table 3-11 Claim Tag Set Register bit assignments ................................................................. 3-15
Table 3-12 Claim Tag Clear Register bit assignments .............................................................. 3-15
Table 3-13 Lock Access Register bit assignments .................................................................... 3-16
Table 3-14 Lock Status Register bit assignments ..................................................................... 3-17
Table 3-15 Authentication Status Register bit assignments ...................................................... 3-18
Table 3-16 Authentication Status Register pairs ....................................................................... 3-18
Table 3-17 Device ID Register bit assignments ........................................................................ 3-18
