Methodologies for Adaptation to Process Variations, Manufacturing
Defects, and Transient Errors in Scaled CMOS
Abstract
VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With CMOS
device dimensions falling below 100 nm, achieving higher performance and packing more
complex functionalities into digital integrated circuits have become easier. However, the scaling
trend poses new challenges to design and process engineers. Such challenges include larger
process parameter variations and the consequent parametric yield loss, ensuring the reliability of
deep sub-micron technologies under soft errors, and reliably fabricating billions of devices on a
die.
The objective of my research has been to develop circuit and system level techniques to address
process variations, transient errors, and the reliability concerns in deeply scaled CMOS
technologies. The proposed techniques can be divided into three parts, highlighted in the next
three sections. The first part addresses the issues related to process variations and proposes
techniques to reduce the variation effects on power and performance. The second part proposes a
novel low-overhead defect-tolerant
approach for CMOS designs capable of efficiently recovering from dozens of defects. The third
section deals with the transient errors and techniques to reduce the effect of transient errors with
minimum hardware or computational overhead.
1. Variation-Tolerant Design
With the increase of process parameter variations in CMOS technologies due to the processing
and masking limitations, power and performance variations become major concerns of circuit
designers. Techniques such as the use of forward/reverse body bias and voltage scaling are
commonly used to bring down the delay and power consumption specifications in the acceptable
range. Variation-aware circuit sizing is another technique used at the design stage to have a more
variation-tolerant circuit.
The key goal of this research is to provide techniques for designing more variation-tolerant
circuits. We propose to attack the problem both at the design stage and at the post-fabrication
stage. The latter requires the feasibility of having ways of specification tuning and a fast and
efficient framework that makes the post-silicon tuning attractive. The summary of the proposed
techniques is as follows:
Variation-Aware Placement [1],[2]: In this work the huge leakage variation problem was
addressed by looking at the effects that the gate placement have in leakage distribution. The work
includes algorithms for the placement of gates in a dual-V circuit to mitigate the large leakage
variation by reducing the variation caused by correlated within-die process variation. The
experimental results on ISCAS benchmark circuits shows how by evenly distributing the low-V
gates (which are more sensitive to variation sources such as the channel length variation) across a
die, one could reduce the sub-threshold leakage variation as compared to the placement technique
with the objective of minimizing wire length. The results show that the sub-threshold leakage
variation is reduced by an average of 17% and maximum of 31%. This obtained with a small
increase in wire length.
Post-Manufacture Tuning Architecture [3]: In this work, an architectural framework for post-
