EFM8SB1小蜜蜂单片机手册Silicon-Labs

EFM8 Sleepy Bee Family

EFM8SB1 Data Sheet

The EFM8SB1, part of the Sleepy Bee family of MCUs, is the

world’s most energy friendly 8-bit microcontrollers with a compre-

hensive feature set in small packages.

These devices offer lowest power consumption by combining innovative low energy tech-

niques and short wakeup times from energy saving modes into small packages, making

them well-suited for any battery operated applications. With an efficient 8051 core, 14

high-quality capacitive sense channels, and precision analog, the EFM8SB1 family is al-

at 24.5 MHz)

• Lowest MCU wake on touch average

current (< 1 μA)

• Lowest sleep current using internal RTC

and supply brownout (< 300 nA)

• Ultra-fast wake up for digital and analog

peripherals (< 2 μs)

• Integrated LDO to maintain ultra-low active

current at all voltages

• Touch pads / key pads

Core / Memory Clock Management

CIP-51 8051 Core

(25 MHz)

Energy Management

Lowest power mode with peripheral operational:

Low Power 20 MHz

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• Memory:

• Power:

• I/O: Up to 17 total multifunction I/O pins:

With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8SB1 devices are truly standalone

EFM8SB1 Data Sheet

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• CIP-51 Core running up to 25 MHz

• Three Internal Oscillators (24.5 MHz, 20 MHz, and 16 kHz)

• SMBus / I2C

• SPI

• UART

• 3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)

• 4 16-bit Timers

• Analog Comparator

• 6-bit current sourc reference

• 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor

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EFM8SB1 Data Sheet

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ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the

device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when

not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little

power when they are not in use.

Table 3.1. Power Modes

Power Mode Details Mode Entry Wake-Up Sources

Normal Core and all peripherals clocked and fully operational — —

Idle • Core halted

• All peripherals clocked and fully operational

• Code resumes execution on wake event

Set IDLE bit in PCON0 Any interrupt

• RTC0 Fail Event

• CS0 Interrupt

• Port Match Event

• Comparator 0 Rising

Edge

Sleep • Most internal power nets shut down

• Select circuits remain powered

• Pins retain state

• All RAM and SFRs retain state

• Code resumes execution on wake event

1. Disable unused ana-

• RTC0 Alarm Event

Edge

3.3 I/O

Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P1.7 can be defined as gen-

eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an

analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7.

• Up to 17 multi-functions I/O pins, supporting digital and analog functions.

• Flexible priority crossbar decoder for digital peripheral assignment.

• Two drive strength settings for each pin.

• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).

• Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).

• 16.4 kHz low-frequency oscillator (LFOSC0) or external RTC 32 kHz crystal.

• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK).

• Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.

EFM8SB1 Data Sheet

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