sparc-leon3

This LEON3 design is tailored to the Xilinx Virtex5 ML510 board --------------------------------------------------------------------- NOTE1: To use LEON/GRLIB on this board with the DDR2SPA controller, you must use unbuffered/unregistered DDR2 memory devices. The devices delivered with the ML510 kit are buffered and cannot be used. NOTE2: The ML510 has a bug that prevents the use of 64 bit DDR2. See description of the DDR2 interface below. Design specifics: * System reset is mapped to the CPU RESET button * The DSU UART is connected to UART 0. The DSU BREAK input is mapped to position 1 on the GPIO DIP switch. When the switch is 'on' the DSU break signal is active. * The DSU error signal is connected to opb_bus_error. When the processor is in error mode the LED will be red. The DSU active signal is connected to plb_bus_error. When the DSU is active the LED will be red. * The serial port is connected to UART 1. * The JTAG DSU interface is enabled and works well with GRMON and Xilinx parallel and USB cables * The GRGPIO port is mapped in the following way: gpio[3:0] : SW5[4:1] / Green LEDs gpio[4] : DVI GPIO gpio[5] : sbr_intr_r (input only) gpio[6] : sbr_nmi_r (input only) gpio[7] : sbr_pwg_rsm_rstj gpio[8] : sbr_ide_rst_b gpio[9] : iic_therm_b (input only) gpio[10] : iic_irq_b (input only) gpio[11] : iic_alert_b (input only) * The sbr_intr_r signal should be used as an interrupt source if the PCI south bridge is used. The GRPCI core is assigned interrupt line 5 and the PCI drivers will trigger on this IRQ. * The DSU registers are located at 0xd0000000. Normally these registers are mapped at 0x90000000. Some software may have hardcoded or default values for 0x90000000. * The APB bridge start address is 0xc0000000. This address is normally 0x80000000 in Leon3/GRLIB designs. Some software may default to, or use hard coded values for, 0x80000000. * The GRETH core is enabled and runs without problems at 100 Mbit. The Ethernet debug link is enabled, default IP is 192.168.0.52. * DDR2 is supported and runs OK at 200 MHz. The default setting is to run the DDR controller on 2x the system clock. This leads to lower latencies. If the CFG_DDR2SP_NOSYNC generic is set to 0 it is possible to specify the DDR frequency via xconfig. When changing frequency, the delay on the data signals might need to be changed too. How to do this is described in the DDR2SPA section of grip.pdf (see description of SDCFG3 register). The ML510 board has the DDR clk 1 inverted (DIMM*_DDR2_CK2_N and DIMM*_DDR2_CK2_P have been flipped). This prevents DDR2SPA from using the full 64-bit interface. Instead the core is instantiated with a 32-bit data width. This means that only half of the available memory on a DIMM will be used. The DDR2 DIMMs shipped with the ML510 use registered DDR2 and only makes use of DIMM*_DDR2_CK0_*. Therefore designs using memory controllers from Xilinx, that support registered DDR2, works with 64-bit memory width. DDR2SPA from GRLIB does not support registered DDR2 at this time and therefore requires all three clocks to be correctly connected. The core can be configured, via xconfig, to use 64-bit data with. Do not select this setting unless you have a modified board. When connecting with GRMON it will set the stack pointer to the top of RAM of the first memory controller. To have an OS access the full memory the stack pointer can be manually set to the end of the second memory controller's area. For the template design the correct switch to GRMON is -stack 0x7ffffff0. * The FLASH memory can be programmed using GRMON * The LEON3 processor can run up to 80 - 90 MHz on the board in the typical configuration. * The design has two I2C masters. One is connected to the main IIC bus and one is connected to the video IIC bus. The I2C master connected to the main bus can be deactivated via xconfig. The I2C master connected to the video IIC bus is instantiated when a VGA core is included. * The SVGACTRL core is enabled and is connected to the DVI transmitter. When one, or both, of the VGA cores is enabled an extra I2C master is automatically instantiated. This I2C master is utilized to initialize the DVI transmitter. A special GRMON command exists to initialize the Chrontel CH7301C. See below for an example. Adjustment of the delay before latching input data may be needed. This can be done using the 'i2c 1 dvi delay [dec|inc]' command. NOTE: If the the VGA cores are disabled the constraints on the VGA clocks must be removed from the leon3mp.ucf file. * SPICTRL is attached to the SPI Flash memory device. To communicate with the memory device, the core needs to be initialized to generate a SPI clock of ~1 MHz. When using GRMON this can be attained with the command 'spi set div16 pm 1'. When using GRMON the "Microchip 25AA640/25LC640" must be selected via the command 'spi flash select'. * The design should be loaded from CompactFlash via System ACE. The FPGA can also be directly programmed with 'make ise-prog-fpga'. Make sure to set the value of SW3 appropriately. * Sample output from GRMON is: grmon -eth -ip 192.168.0.52 GRMON LEON debug monitor v1.1.32 Copyright (C) 2004-2008 Gaisler Research - all rights reserved. For latest updates, go to http://www.gaisler.com/ Comments or bug-reports to support@gaisler.com ethernet startup. Device ID: : 0x510 GRLIB build version: 3293 initialising ........................ detected frequency: 80 MHz Component Vendor LEON3 SPARC V8 Processor Gaisler Research AHB Debug UART Gaisler Research AHB Debug JTAG TAP Gaisler Research SVGA frame buffer Gaisler Research GR Ethernet MAC Gaisler Research Fast 32-bit PCI Bridge Gaisler Research PCI/AHB DMA controller Gaisler Research DDR2 Controller Gaisler Research DDR2 Controller Gaisler Research LEON3 Debug Support Unit Gaisler Research LEON2 Memory Controller European Space Agency AHB/APB Bridge Gaisler Research System ACE I/F Controller Gaisler Research AMBA Wrapper for System Monitor Gaisler Research Generic APB UART Gaisler Research Multi-processor Interrupt Ctrl Gaisler Research Modular Timer Unit Gaisler Research AMBA Wrapper for OC I2C-master Gaisler Research General purpose I/O port Gaisler Research AMBA Wrapper for OC I2C-master Gaisler Research SPI Controller Gaisler Research PCI trace buffer Gaisler Research PCI Arbiter European Space Agency AHB status register Gaisler Research Use command 'info sys' to print a detailed report of attached cores grlib> inf sys 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) ahb master 0 01.01:007 Gaisler Research AHB Debug UART (ver 0x0) ahb master 1 apb: c0000700 - c0000800 baud rate 115200, ahb frequency 80.00 02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0) ahb master 2 03.01:063 Gaisler Research SVGA frame buffer (ver 0x0) ahb master 3 apb: c0000e00 - c0000f00 clk0: 25.00 MHz clk1: 25.00 MHz clk2: 40.00 MHz clk3: 65.00 MHz 04.01:01d Gaisler Research GR Ethernet MAC (ver 0x0) ahb master 4, irq 4 apb: c0000b00 - c0000c00 edcl ip 192.168.0.52, buffer 2 kbyte 05.01:014 Gaisler Research Fast 32-bit PCI Bridge (ver 0x0) ahb master 5, irq 5 ahb: 80000000 - c0000000 ah