REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
REM
vivado -log mb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source mb.tcl
project_8.zip
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project_8.zip （49个子文件） 
vivado_14636.backup.log 10KB
.Xil project_8.sim project_8.hw hw_1 wave project_8.lpr 478B vivado.log 6KB project_8.runs impl_1 init_design.pb 2KB phys_opt_design.pb 3KB write_bitstream.pb 7KB route_design.pb 12KB opt_design.pb 14KB place_design.pb 15KB .jobs vrs_config_1.xml 474B vrs_config_3.xml 474B vrs_config_4.xml 665B vrs_config_5.xml 495B vrs_config_2.xml 474B vrs_config_6.xml 474B synth_1 runme.bat 305B .vivado.begin.rst 219B .vivado.end.rst 0B runme.log 17KB rundef.js 1KB
htr.txt 456B mb.dcp 36KB .Xil mb_propImpl.xdc 2KB incr_synth_reason.pb 57B mb_utilization_synth.pb 276B project.wdf 4KB __synthesis_is_complete__ 0B mb_utilization_synth.rpt 8KB .Vivado_Synthesis.queue.rst 0B vivado.jou 829B vivado.pb 22KB gen_run.xml 3KB mb.tcl 5KB runme.sh 1KB mb.vds 17KB ISEWrap.js 8KB ISEWrap.sh 2KB vivado.jou 904B project_8.cache compile_simlib riviera vcs modelsim xcelium activehdl questa ip 2023.2 wt webtalk_pa.xml 1KB project.wpc 121B synthesis_details.wdf 100B synthesis.wdf 7KB vivado_14636.backup.jou 898B project_8.xpr 12KB project_8.ip_user_files project_8.srcs utils_1 imports synth_1 mb.dcp 37KB constrs_1 new mb.xdc 2KB sources_1 new time_counter.v 2KB smg_ip_model.v 2KB mb.v 946B资源评论
