/*
* Copyright (c) 2010 Broadcom Corporation
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/cordic.h>
#include <brcm_hw_ids.h>
#include <aiutils.h>
#include <chipcommon.h>
#include <pmu.h>
#include <d11.h>
#include <phy_shim.h>
#include "phy_int.h"
#include "phy_hal.h"
#include "phy_radio.h"
#include "phyreg_n.h"
#include "phytbl_n.h"
#include "soc.h"
#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \
read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
((core == PHY_CORE_0) ? \
radio_type##_##jspace##0 : \
radio_type##_##jspace##1))
#define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \
write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
((core == PHY_CORE_0) ? \
radio_type##_##jspace##0 : \
radio_type##_##jspace##1), value)
#define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \
write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value)
#define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \
read_radio_reg(pi, ((core == PHY_CORE_0) ? \
radio_type##_##jspace##0##_##reg_name : \
radio_type##_##jspace##1##_##reg_name))
#define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \
write_radio_reg(pi, ((core == PHY_CORE_0) ? \
radio_type##_##jspace##0##_##reg_name : \
radio_type##_##jspace##1##_##reg_name), \
value)
#define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \
read_radio_reg(pi, ((core == PHY_CORE_0) ? \
radio_type##_##reg_name##_##jspace##0 : \
radio_type##_##reg_name##_##jspace##1))
#define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \
write_radio_reg(pi, ((core == PHY_CORE_0) ? \
radio_type##_##reg_name##_##jspace##0 : \
radio_type##_##reg_name##_##jspace##1), \
value)
#define NPHY_ACI_MAX_UNDETECT_WINDOW_SZ 40
#define NPHY_ACI_CHANNEL_DELTA 5
#define NPHY_ACI_CHANNEL_SKIP 4
#define NPHY_ACI_40MHZ_CHANNEL_DELTA 6
#define NPHY_ACI_40MHZ_CHANNEL_SKIP 5
#define NPHY_ACI_40MHZ_CHANNEL_DELTA_GE_REV3 6
#define NPHY_ACI_40MHZ_CHANNEL_SKIP_GE_REV3 5
#define NPHY_ACI_CHANNEL_DELTA_GE_REV3 4
#define NPHY_ACI_CHANNEL_SKIP_GE_REV3 3
#define NPHY_NOISE_NOASSOC_GLITCH_TH_UP 2
#define NPHY_NOISE_NOASSOC_GLITCH_TH_DN 8
#define NPHY_NOISE_ASSOC_GLITCH_TH_UP 2
#define NPHY_NOISE_ASSOC_GLITCH_TH_DN 8
#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_UP 2
#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_DN 8
#define NPHY_NOISE_NOASSOC_ENTER_TH 400
#define NPHY_NOISE_ASSOC_ENTER_TH 400
#define NPHY_NOISE_ASSOC_RX_GLITCH_BADPLCP_ENTER_TH 400
#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX 44
#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX_REV_7 56
#define NPHY_NOISE_NOASSOC_CRSIDX_INCR 16
#define NPHY_NOISE_ASSOC_CRSIDX_INCR 8
#define NPHY_IS_SROM_REINTERPRET NREV_GE(pi->pubpi.phy_rev, 5)
#define NPHY_RSSICAL_MAXREAD 31
#define NPHY_RSSICAL_NPOLL 8
#define NPHY_RSSICAL_MAXD (1<<20)
#define NPHY_MIN_RXIQ_PWR 2
#define NPHY_RSSICAL_W1_TARGET 25
#define NPHY_RSSICAL_W2_TARGET NPHY_RSSICAL_W1_TARGET
#define NPHY_RSSICAL_NB_TARGET 0
#define NPHY_RSSICAL_W1_TARGET_REV3 29
#define NPHY_RSSICAL_W2_TARGET_REV3 NPHY_RSSICAL_W1_TARGET_REV3
#define NPHY_CALSANITY_RSSI_NB_MAX_POS 9
#define NPHY_CALSANITY_RSSI_NB_MAX_NEG -9
#define NPHY_CALSANITY_RSSI_W1_MAX_POS 12
#define NPHY_CALSANITY_RSSI_W1_MAX_NEG (NPHY_RSSICAL_W1_TARGET - \
NPHY_RSSICAL_MAXREAD)
#define NPHY_CALSANITY_RSSI_W2_MAX_POS NPHY_CALSANITY_RSSI_W1_MAX_POS
#define NPHY_CALSANITY_RSSI_W2_MAX_NEG (NPHY_RSSICAL_W2_TARGET - \
NPHY_RSSICAL_MAXREAD)
#define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f)))
#define NPHY_RSSI_NB_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_NB_MAX_POS) || \
((x) < NPHY_CALSANITY_RSSI_NB_MAX_NEG))
#define NPHY_RSSI_W1_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W1_MAX_POS) || \
((x) < NPHY_CALSANITY_RSSI_W1_MAX_NEG))
#define NPHY_RSSI_W2_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W2_MAX_POS) || \
((x) < NPHY_CALSANITY_RSSI_W2_MAX_NEG))
#define NPHY_IQCAL_NUMGAINS 9
#define NPHY_N_GCTL 0x66
#define NPHY_PAPD_EPS_TBL_SIZE 64
#define NPHY_PAPD_SCL_TBL_SIZE 64
#define NPHY_NUM_DIG_FILT_COEFFS 15
#define NPHY_PAPD_COMP_OFF 0
#define NPHY_PAPD_COMP_ON 1
#define NPHY_SROM_TEMPSHIFT 32
#define NPHY_SROM_MAXTEMPOFFSET 16
#define NPHY_SROM_MINTEMPOFFSET -16
#define NPHY_CAL_MAXTEMPDELTA 64
#define NPHY_NOISEVAR_TBLLEN40 256
#define NPHY_NOISEVAR_TBLLEN20 128
#define NPHY_ANARXLPFBW_REDUCTIONFACT 7
#define NPHY_ADJUSTED_MINCRSPOWER 0x1e
/* 5357 Chip specific ChipControl register bits */
#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
#define NPHY_CAL_TSSISAMPS 64
#define NPHY_TEST_TONE_FREQ_40MHz 4000
#define NPHY_TEST_TONE_FREQ_20MHz 2500
#define MAX_205x_RCAL_WAITLOOPS 10000
#define NPHY_RXCAL_TONEAMP 181
#define NPHY_RXCAL_TONEFREQ_40MHz 4000
#define NPHY_RXCAL_TONEFREQ_20MHz 2000
#define TXFILT_SHAPING_OFDM20 0
#define TXFILT_SHAPING_OFDM40 1
#define TXFILT_SHAPING_CCK 2
#define TXFILT_DEFAULT_OFDM20 3
#define TXFILT_DEFAULT_OFDM40 4
struct nphy_iqcal_params {
u16 txlpf;
u16 txgm;
u16 pga;
u16 pad;
u16 ipa;
u16 cal_gain;
u16 ncorr[5];
};
struct nphy_txiqcal_ladder {
u8 percent;
u8 g_env;
};
struct nphy_ipa_txcalgains {
struct nphy_txgains gains;
bool useindex;
u8 index;
};
struct nphy_papd_restore_state {
u16 fbmix[2];
u16 vga_master[2];
u16 intpa_master[2];
u16 afectrl[2];
u16 afeoverride[2];
u16 pwrup[2];
u16 atten[2];
u16 mm;
};
struct nphy_ipa_txrxgain {
u16 hpvga;
u16 lpf_biq1;
u16 lpf_biq0;
u16 lna2;
u16 lna1;
s8 txpwrindex;
};
#define NPHY_IPA_RXCAL_MAXGAININDEX (6 - 1)
static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_5GHz[] = {
{0, 0, 0, 0, 0, 100},
{0, 0, 0, 0, 0, 50},
{0, 0, 0, 0, 0, -1},
{0, 0, 0, 3, 0, -1},
{0, 0, 3, 3, 0, -1},
{0, 2, 3, 3, 0, -1}
};
static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_2GHz[] = {
{0, 0, 0, 0, 0, 128},
{0, 0, 0, 0, 0, 70},
{0, 0, 0, 0, 0, 20},
{0, 0, 0, 3, 0, 20},
{0, 0, 3, 3, 0, 20},
{0, 2, 3, 3, 0, 20}
};
static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_5GHz_rev7[] = {
{0, 0, 0, 0, 0, 100},
{0, 0, 0, 0, 0, 50},
{0, 0, 0, 0, 0, -1},
{0, 0, 0, 3, 0, -1},
{0, 0, 3, 3, 0, -1},
{0, 0, 5, 3, 0, -1}
};
static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_2GHz_rev7[] = {
{0, 0, 0, 0, 0, 10},
{0, 0, 0, 1, 0, 10},
{0, 0, 1, 2, 0, 10},
{0, 0, 1, 3, 0, 10},
{0, 0, 4, 3, 0, 10},
{0, 0, 6, 3, 0, 10}
};
enum {
NPHY_RXCAL_GAIN_INIT = 0,
NPHY_RXCAL_GAIN_UP,
NPHY_RXCAL_GAIN_DOWN
};
#define wlc_phy_get_papd_nphy(pi) \
(read_phy_reg((pi), 0x1e7) & \
((0x1 << 15) | \
(0x1 << 14) | \
(0x1 << 13)))
static const u16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = {
{-377, 137, -407, 208, -1527, 956, 93, 186, 93,
230, -44, 230, 201, -191, 201},
{-77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5,
26, 34, -32, 34},
{-360, 164, -376, 164, -1533, 576, 308, -314, 308,
121, -73, 121, 91, 124, 91},
{-295, 200, -363, 142, -1391, 826, 151, 301, 151,
151, 301,
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cloud-kernel-devel-4.19.zip
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cloud-kernel-devel-4.19.zip (2000个子文件)
phy_n.c 917KB
nls_cp949.c 855KB
nls_cp936.c 682KB
lpfc_sli.c 589KB
nls_cp950.c 580KB
radio_2056.c 509KB
nls_cp932.c 480KB
tg3.c 469KB
intel_display.c 458KB
chip.c 452KB
message.c 435KB
nl80211.c 428KB
bnx2x_main.c 422KB
vmx.c 412KB
bnx2x_link.c 410KB
i40e_main.c 402KB
test_verifier.c 388KB
lpfc_init.c 372KB
init301.c 351KB
drxj.c 350KB
advansys.c 346KB
ppc-opc.c 330KB
ipw2200.c 324KB
mpt3sas_scsih.c 322KB
fair.c 321KB
ixgbe_main.c 306KB
rt2800lib.c 304KB
ipr.c 302KB
lpfc_els.c 301KB
nm256_coef.c 301KB
extent-tree.c 301KB
wmi.c 300KB
aic79xx_core.c 292KB
t4_hw.c 291KB
halhwimg8822b_rf.c 291KB
inode.c 288KB
core.c 285KB
ql4_os.c 283KB
intel_pm.c 280KB
cik.c 280KB
patch_realtek.c 273KB
hpsa.c 271KB
qib_iba7322.c 264KB
thinkpad_acpi.c 263KB
nfs4proc.c 262KB
DAC960.c 259KB
igb_main.c 257KB
si_dpm.c 254KB
zc3xx.c 254KB
x86.c 253KB
gfx_v8_0.c 252KB
md.c 247KB
socket.c 247KB
dev.c 244KB
page_alloc.c 242KB
raid5.c 240KB
bnxt.c 239KB
s2io.c 238KB
mptbase.c 236KB
megaraid_sas_base.c 235KB
ips.c 231KB
memcontrol.c 230KB
si_dpm.c 229KB
qed_debug.c 229KB
niu.c 229KB
synclink.c 229KB
qla_init.c 227KB
ipw2100.c 225KB
io_uring.c 222KB
ufshcd.c 218KB
airo.c 218KB
mac.c 217KB
bnx2.c 216KB
clk-exynos5433.c 216KB
netdev.c 215KB
main.c 214KB
cx25840-core.c 211KB
aic7xxx_core.c 211KB
ncr53c8xx.c 210KB
patch_ca0132.c 209KB
saa7134-cards.c 208KB
dce_calcs.c 208KB
si.c 207KB
trace.c 207KB
sm_statefuns.c 204KB
mpt3sas_base.c 204KB
nfs4xdr.c 203KB
rtw_mlme_ext.c 202KB
pfc-r8a7795.c 202KB
ef10.c 201KB
smartpqi_init.c 201KB
ci_dpm.c 200KB
pfc-r8a7796.c 200KB
spectrum_router.c 200KB
volumes.c 200KB
qla_target.c 199KB
phy_n.c 199KB
lpfc_attr.c 199KB
nfs4state.c 198KB
pinctrl-atlas7.c 198KB
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