基本sync单元
Reg r_data_in;
Reg r_ sync_data_1d;
Reg r_sync_data_2d;
Always @(posedge clk_in or negedge rstn_in)
if(rstn_in) r_data_in <= 1’b0;
else r_data_in <= data_in;
Always @(posedge clk out or negedge rstn_out)
if(~rstn_out) r_sync_data_1d <= 1’b0;
else r_sync_data_1d <= r_data_in;
Always@(posedge clk_out or negedge rstn_out)
if(~rstn_out) r_sync_data_2d <= 1’b0;
else r_sync_data_2d <= r_sync_data_1d;
