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DDR4 SDRAMK4A4G165WF datasheet
Preliminary Rev. 0.9
Table Of Contents
4Gb F-die DDR4 SDRAM x16 only
1. ORDERING INFORMATION ............................................................................................................................................................... 4
2. KEY FEATURES ................................................................................................................................................................................. 4
3. PACKAGE PINOUT/MECHANICAL DIMENSION & ADDRESSING .................................................................................................. 5
3.1 x16 Package Pinout (Top view): 96ball FBGA Package.................................................................................................................5
3.2 FBGA Package Dimension (x16)....................................................................................................................................................6
4. INPUT/OUTPUT FUNCTIONAL DESCRIPTION ................................................................................................................................ 7
5. DDR4 SDRAM ADDRESSING ............................................................................................................................................................ 9
6. ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................................... 10
6.1 DRAM Component Operating Temperature Range........................................................................................................................10
7. AC & DC OPERATING CONDITIONS ................................................................................................................................................ 10
8. AC AND DC INPUT MEASUREMENT LEVELS ................................................................................................................................. 11
8.1 AC And DC Logic Input Levels for Single-Ended Signals...............................................................................................................11
8.2 AC and DC Input Measurement Levels: VREF Tolerances............................................................................................................11
8.3 AC and DC Logic Input Levels for Differential Signals ...................................................................................................................12
8.3.1. Differential Signals Definition ..................................................................................................................................................12
8.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ......................................................................................................12
8.3.3. Single-ended Requirements for Differential Signals ...............................................................................................................13
8.3.4. Address, Command and Control Overshoot and Undershoot specifications..........................................................................14
8.3.5. Clock Overshoot and Undershoot Specifications....................................................................................................................15
8.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications........................................................................................16
8.4 Slew Rate Definitions......................................................................................................................................................................17
8.4.1. Slew Rate Definitions for Differential Input Signals (CK) ........................................................................................................17
8.4.2. Slew Rate Definition for Single-ended Input Signals (CMD/ADD) ..........................................................................................18
8.5 Differential Input Cross Point Voltage.............................................................................................................................................19
8.6 CMOS rail to rail Input Levels .........................................................................................................................................................20
8.6.1. CMOS rail to rail Input Levels for RESET_n ...........................................................................................................................20
8.7 AC and DC Logic Input Levels for DQS Signals.............................................................................................................................21
8.7.1. Differential signal definition .....................................................................................................................................................21
8.7.2. Differential swing requirements for DQS (DQS_t - DQS_c)....................................................................................................21
8.7.3. Peak voltage calculation method ............................................................................................................................................22
8.7.4. Differential Input Cross Point Voltage .....................................................................................................................................23
8.7.5. Differential Input Slew Rate Definition ....................................................................................................................................24
9. AC AND DC OUTPUT MEASUREMENT LEVELS ............................................................................................................................. 25
9.1 Output Driver DC Electrical Characteristics....................................................................................................................................25
9.1.1. Output Driver Temperature and Voltage Sensitivity................................................................................................................27
9.1.2. Alert_n output Drive Characteristic .........................................................................................................................................27
9.1.3. Output Driver Characteristic of Connectivity Test (CT) Mode.................................................................................................28
9.2 Single-ended AC & DC Output Levels............................................................................................................................................29
9.3 Differential AC & DC Output Levels................................................................................................................................................29
9.4 Single-ended Output Slew Rate .....................................................................................................................................................30
9.5 Differential Output Slew Rate .........................................................................................................................................................31
9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode .................................................................................................32
9.7 Test Load for Connectivity Test Mode Timing ................................................................................................................................33
10. SPEED BIN ....................................................................................................................................................................................... 34
10.1 Speed Bin Table Note...................................................................................................................................................................41
11. IDD AND IDDQ SPECIFICATION PARAMETERS AND TEST CONDITIONS ................................................................................. 42
11.1 IDD, IPP and IDDQ Measurement Conditions..............................................................................................................................42
11.2 4Gb DDR4 SDRAM F-die IDD SPECIFICATION TABLE.............................................................................................................57
12. INPUT/OUTPUT CAPACITANCE ..................................................................................................................................................... 59
13. ELECTRICAL CHARACTERISTICS & AC TIMING .......................................................................................................................... 61
13.1 Reference Load for AC Timing and Output Slew Rate .................................................................................................................61
13.2 tREFI.............................................................................................................................................................................................61
13.3 Clock Specification .......................................................................................................................................................................62
13.3.1. Definition for tCK(abs)...........................................................................................................................................................62
13.3.2. Definition for tCK(avg)...........................................................................................................................................................62
13.3.3. Definition for tCH(avg) and tCL(avg)....................................................................................................................................62
13.3.4. Definition for tERR(nper).......................................................................................................................................................62
14. TIMING PARAMETERS BY SPEED GRADE ................................................................................................................................... 63
14.1 Rounding Algorithms ...................................................................................................................................................................69
14.2 The DQ input receiver compliance mask for voltage and timing ..................................................................................................70
14.3 Command, Control, and Address Setup, Hold, and Derating .......................................................................................................74
14.4 DDR4 Function Matrix ..................................................................................................................................................................76
