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FN8179 Rev.2.00 Page 1 of 16

December 21, 2009

FN8179

Rev.2.00

December 21, 2009

X9315

Low Noise, Low Power, 32 Taps Digitally Controlled Potentiometer

(XDCP™)

DATASHEET

The Intersil X9315 is a digitally controlled potentiometer

(XDCP). The device consists of a resistor array, wiper

switches, a control section, and nonvolatile memory. The

wiper position is controlled by a 3-wire interface.

The potentiometer is implemented by a resistor array

composed of 31 resistive elements and a wiper switching

network. Between each element and at either end are tap

points accessible to the wiper terminal. The position of the

wiper element is controlled by the CS

, U/D, and INC inputs.

The position of the wiper can be stored in nonvolatile

memory and then be recalled upon a subsequent power-up

operation.

The device can be used as a three-terminal potentiometer or

as a two-terminal variable resistor in a wide variety of

applications including:

• Control

• Parameter Adjustments

• Signal Processing

Features

• Solid-state potentiometer

• 3-wire serial interface

• 32 wiper tap points

- Wiper position stored in nonvolatile memory and

recalled on power-up

• 31 resistive elements

- Temperature compensated

- End to end resistance range ± 20%

- Terminal voltage, 0 to V

• Low power CMOS

-V

= 2.7V or 5V

- Active current, 80/400µA max.

- Standby current, 5µA max.

• High reliability

- Endurance, 100,000 data changes per bit

- Register data retention, 100 years

•R

TOTAL

values = 10k, 50k, 100k

• Packages

- 8 Ld SOIC, MSOP and PDIP

• Pb-free available (RoHS compliant)

Block Diagram

5-Bit

Up/Down

Counter

5-Bit

Nonvolatile

Memory

Store and

Recall

Control

Circuitry

One

Decoder

Resistor

Array

U/D

INC

Transfer

Gates

Thirty

Control

and

Memory

Up/Down

(U/D

)

Increment

(INC

)

Device Select

(CS

)

(Supply Voltage)

(Ground)

General

Detailed

Two

X9315

FN8179 Rev.2.00 Page 2 of 16

December 21, 2009

Ordering Information

PART NUMBER PART MARKING

LIMITS

(V)

TOTAL

(k)

TEMP RANGE

(°C) PACKAGE

PKG.

DWG. #

X9315WMZ (Note 2) DDT 5 ±10% 10 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMZT1 (Notes 1, 2) DDT 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMIT2 (Note 1) AAX -40 to 85 8 Ld MSOP M8.118

X9315WMIZ (Note 2) AKW -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WMIZT1 (Notes 1, 2) AKW -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WP X9315WP 0 to 70 8 Ld PDIP MDP0031

X9315WST1 (Note 1) X9315W 0 to 70 8 Ld SOIC M8.15E

X9315WSZ (Note 2) X9315W Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSZT1 (Notes 1, 2) X9315W Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSI X9315W I -40 to 85 8 Ld SOIC M8.15E

X9315WSIT1 (Note 1) X9315W I -40 to 85 8 Ld SOIC M8.15E

X9315WSIZ (Note 2) X9315W ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315WSIZT1 (Notes 1, 2) X9315W ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315UMZ (Note 2) DDS 50 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMZT1 (Notes 1, 2) DDS 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMI AEB -40 to 85 8 Ld MSOP M8.118

X9315UMIT1 (Notes 1, 2) AEB -40 to 85 8 Ld MSOP M8.118

X9315UMIZ (Note 2) DDR -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315UMIZT1 (Notes 1, 2) DDR -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315UST2 (Note 1) X9315U 0 to 70 8 Ld SOIC M8.15E

X9315USZ (Note 2) X9315U Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USZT1 (Notes 1, 2) X9315U Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USIZ (Note 2) X9315U ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315USIZT1 (Notes 1, 2) X9315U ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TMZ (Note 2) DDN 100 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMZT1 (Notes 1, 2) DDN 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMIZ (Note 2) DDL -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TMIZT1 (Notes 1, 2) DDL -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TSZ (Note 2) X9315T Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSZT1 (Notes 1, 2) X9315T Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSIZ (Note 2) X9315T ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TSIZT1 (Notes 1, 2) X9315T ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315WMZ-2.7 (Note 2) AOI 2.7 to 5.5 10 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMZ-2.7T1 (Notes 1, 2) AOI 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMI-2.7T2 (Note 1) AAV -40 to 85 8 Ld MSOP M8.118

X9315WMIZ-2.7 (Note 2) AKX -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WMIZ-2.7T1 (Notes 1, 2) AKX -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WS-2.7 X9315W F 0 to 70 8 Ld SOIC M8.15E

X9315

FN8179 Rev.2.00 Page 3 of 16

December 21, 2009

X9315WS-2.7T1 (Note 1) X9315W F 2.7 to 5.5 10 0 to 70 8 Ld SOIC M8.15E

X9315WSZ-2.7 (Note 2) X9315W ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSZ-2.7T1 (Notes 1, 2) X9315W ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSI-2.7T1 (Note 1) X9315W G -40 to 85 8 Ld SOIC M8.15E

X9315WSIZ-2.7 (Note 2) X9315W ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315WSIZ-2.7T1 (Notes 1, 2) X9315W ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315UMZ-2.7 (Note 2) AKU 50 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMZ-2.7T1 (Notes 1, 2) AKU 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMIZ-2.7 (Note 2) AJG -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315UMIZ-2.7T1 (Notes 1, 2) AJG -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315US-2.7T2 (Note 1) X9315U F 0 to 70 8 Ld SOIC M8.15E

X9315USZ-2.7 (Note 2) X9315U ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USZ-2.7T1 (Notes 1, 2) X9315U ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USI-2.7 X9315U G -40 to 85 8 Ld SOIC M8.15E

X9315USIZ-2.7 (Note 2) X9315U ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315USIZ-2.7T1 (Notes 1, 2) X9315U ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TMZ-2.7 (Note 2) DDP 100 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMZ-2.7T1 (Notes 1, 2) DDP 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMI-2.7T1 (Note 1) ADY -40 to 85 8 Ld MSOP M8.118

X9315TMIZ-2.7 (Note 2) DDM -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TMIZ-2.7T1 (Notes 1, 2) DDM -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TSZ-2.7 (Note 2) X9315T ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSZ-2.7T1 (Notes 1, 2) X9315T ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSIZ-2.7 (Note 2) X9315T ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TSIZ-2.7T1 (Notes 1, 2) X9315T ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

Ordering Information (Continued)

PART NUMBER PART MARKING

LIMITS

(V)

TOTAL

(k)

TEMP RANGE

(°C) PACKAGE

PKG.

DWG. #

X9315

FN8179 Rev.2.00 Page 4 of 16

December 21, 2009

Pin Configuration

X9315

(8 LD MSOP, SOIC, PDIP)

TOP VIEW

Pin Description

and R

The high (R

) and low (R

) terminals of the X9315 are

equivalent to the fixed terminals of a mechanical

potentiometer. The minimum voltage is V

and the maximum

is V

. The terminology of R

and R

references the

relative position of the terminal in relation to wiper movement

direction selected by the U/D

input, and not the voltage

potential on the terminal.

is the wiper terminal and is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the control inputs. The

wiper terminal series resistance is typically 200 at V

= 5V.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement

and whether the counter is incremented or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will

move the wiper and either increment or decrement the counter

in the direction indicated by the logic level on the U/D

input.

Chip Select (CS)

The device is selected when the CS input is LOW. The current

counter value is stored in nonvolatile memory when CS

returned HIGH while the INC

input is also HIGH. After the store

operation is complete the X9315 will be placed in the low

power standby mode until the device is selected once again.

Principles of Operation

There are three sections of the X9315: the input control,

counter and decode section; the nonvolatile memory; and the

resistor array. The input control section operates just like an

up/down counter. The output of this counter is decoded to turn

on a single electronic switch connecting a point on the resistor

array to the wiper output. Under the proper conditions the

contents of the counter can be stored in nonvolatile memory

and retained for future use. The resistor array is comprised of

31 individual resistors connected in series. At either end of the

array and between each resistor is an electronic switch that

transfers the connection at that point to the wiper.

The wiper, when at either fixed terminal, acts like its

mechanical equivalent and does not move beyond the last

position. That is, the counter does not wrap around when

clocked to either extreme.

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions. If

the wiper is moved several positions, multiple taps are

connected to the wiper for t

(INC to V

change). The

TOTAL

value for the device can temporarily be reduced by a

significant amount if the wiper is moved several positions.

When the device is powered-down, the last wiper position

stored will be maintained in the nonvolatile memory. When

power is restored, the contents of the memory are recalled and

the wiper is set to the value last stored.

Instructions and Programming

The INC, U/D and CS inputs control the movement of the wiper

along the resistor array. With CS

set LOW the device is

selected and enabled to respond to the U/D

and INC inputs.

HIGH to LOW transitions on INC

will increment or decrement

(depending on the state of the U/D

input) a five bit counter. The

output of this counter is decoded to select one of thirty two

wiper positions along the resistive array.

The value of the counter is stored in nonvolatile memory

whenever CS

transitions HIGH while the INC input is also

HIGH.

The system may select the X9315, move the wiper and

deselect the device without having to store the latest wiper

position in nonvolatile memory. After the wiper movement is

performed as described above and once the new position is

reached, the system must keep INC

LOW while taking CS

HIGH. The new wiper position will be maintained until changed

by the system or until a power-up/down cycle recalled the

previously stored data.

This procedure allows the system to always power-up to a

preset value stored in nonvolatile memory; then during system

operation minor adjustments could be made. The adjustments

Pin Names

SYMBOL DESCRIPTION

High terminal

Wiper terminal

Low terminal

Ground

Supply voltage

U/D

Up/Down control input

INC

Increment control input

CS Chip Select control input

INC

U/D

X9315

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