基于Cadence Virtuoso的数模混合仿真教程

数模混合仿真教程

COOK BOOK of AMS FLOW (based on

Cadence Virtuoso)

Chapter 6. Flow to run AMS with SW config .................................................................................. 28

Chapter 7. Sim Results Saving and Ploting ..................................................................................... 33

Chapter 8. Flow to setup scan mode AMS sim .............................................................................. 39

Chapter 9. Useful Tips ............................................................................................................................ 43

Chapter 1. Introduction

The document describes the flow of setting up analog mixed signal simulation TB and

digital content, and as a single process, the analog engine and digital engine share the same

memory accessed, where much benefit is gained as no inter process communication is

needed.

There are two usage model for Spectre AMS designer, one is in graphic user interface,

generally name AVUM（AMS Virtuoso Use Model）,shown as Figure1, it starts from analog

schematic input, building config view in hierarchy editor, netlisting(UNL) and running

simulation in ADE/ADEXL/ADE Explorer/Assembler, which is quite friendly for analog designer

and generally suitable for analog block level simulation or analog-centric(analog on top)

design; another usage model is AXUM(AMS Xcelium Use Model), Figure 2, it is text based flow

and almost all running in command line(except config view is generally created in virtuoso),

Figure 2

Building config view is a key step in AMS simulation, it specifies which view is used for

each cell in the design hierarchy. Generally speaking, analog cells use schematic view or spice

netlist, and digital cells use verilog/systemverilog/VHDL view as it is, and for those frequent

toggling blocks in analog domain, like osc/charge pump/communication IO, simplified

schematic/behavior models will be used, so that the whole simulation performance is

acceptable for chip top functional verification.

2. Create config view:

1) Choose schematic view in the Configuration

2) Select AMS template,

3) Input KUNS01_ANA to lib list

4) Put schematic before Verilog/functional view in view list