An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed,
vendor-defined functionality of an ASIC (application-specific integrated circuit) chip, you can
configure and reconfigure the logic on FPGAs for your specific application. FPGAs are used
in applications where either the cost of developing and fabricating an ASIC is prohibitive, or
the hardware must be reconfigured after being placed into service. The flexible,
software-programmable architecture of FPGAs offer benefits such as high-performance
execution of custom algorithms, precise timing and synchronization, rapid decision making,
and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as
instruments, consumer electronics, automobiles, aircraft, copy machines, and
application-specific computer hardware. While FPGAs are often used in industrial control
products, FPGA functionality has not previously been made accessible to industrial control
engineers. Defining FPGAs has historically required expertise using HDL programming or
complex design tools used more by hardware design engineers than by control
engineers.Within the test-fixture the tx output of the transmitter module is looped back to the r
x input of the receiver module. This allows the transmitter module to be used as test signal ge
nerator for the receiver module. Data can be written in parallel format to the transmitter modu
le and looped back in serial format to the rx input of the receiver module, and data received ca
n finally be read out in parallel format from the receiver module. In order to automate the testi
ng of the UART as much as possible, tree independent Verilog tasks were written as follows.
The Verilog task“write_to_transmitter”
holds all necessary statements required to generate a single parallel data write sequence to the
transmitter module. Data that are written to the transmitter upon execution of the
“write_to_transmitter”
task, get latched internal to the test-fixture for later analysis. The Verilog task
“read_out_receiver”
holds all necessary statements required to generate a single parallel data read out sequence fr
om the receiver module. Data that are read out of the receiver upon execution of the
“read_out_receiver”
task, get latched internal to the test-fixture for later analysis. The Verilog task
“compare_data”
holds all necessary statements required to compare the previous data written to the transmitte
r module, to the corresponding and most recent data received and read out from the receive r
module. If any discrepancy occurs, the “compare_data”
task flags for an error by writing out the data values that were written to the transmitter modu
le, as well as the corresponding data values that were received by and read out from the receiv
er module. The simulation is immediately stopped by the “compare_data”
task if any discrepancy occurs. Besides the tree above mentioned Verilog tasks, the test-fixtur
e holds the statements to generate the mclkx16, the master reset signals as well as the
“tx to rx”
loop back feature. The statements are considered trivial, and will not be illustrated here, but c
an be referred to within the test-fixture itself. The core of the test-fixture is a behavioral level
“for loop”
that executes the tree above mentioned Verilog tasks in order to write all possible data combi
nations to the transmitter and verify that same data gets properly received by the receiver. The
