外文翻译-中英文对照AVR单片机.docx

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access memories, perform calculations, control peripherals, and handle interrupts.

Architectural Overview Figure 3. Block Diagram of the AVR MCU Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the program

memory are executed with a single level pipelining. While one instruction is being executed,

the next instruction is pre-fetched from the program memory. This concept

enables instructions to be executed in every clock cycle. The program memory is In-

System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

memory. These added function registers are the 16-bit X-, Y-, and Z-register,

described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant

and a register. Single register operations can also be executed in the ALU. After

Flash

Program

Memory

Instruction

Register

Instruction

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

9

ATmega16(L)

the Application Program section. Both sections have dedicated Lock bits for write and

read/write protection. The SPM instruction that writes into the Application Flash memory

section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is

stored on the Stack. The Stack is effectively allocated in the general data SRAM, and

consequently the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O

space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as

the Data Space locations following those of the Register File, $20 - $5F.

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general

purpose working registers. Within a single clock cycle, arithmetic operations between

general purpose registers or between a register and an immediate are executed. The

ALU operations are divided into three main categories – arithmetic, logical, and bit-functions.

Some implementations of the architecture also provide a powerful multiplier

supporting both signed/unsigned multiplication and fractional format. See the “Instruction

remove the need for using the dedicated compare instructions, resulting in faster and

more compact code.

The Status Register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

10 ATmega16(L)

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual

interrupt enable control is then performed in separate control registers. If the Global

Interrupt Enable Register is cleared, none of the interrupts are enabled independent of

the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt

has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit

can also be set and cleared by the application with the SEI and CLI instructions, as

described in the instruction set reference.

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See

the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See

the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

“Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

11

ATmega16(L)

General Purpose

Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers,

and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping

them directly into the first 32 locations of the user Data Space. Although not being physically

implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to

index any register in the file.

These registers are 16-bit address pointers for indirect addressing of the Data Space.

The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed

automatic increment, and automatic decrement (see the Instruction Set

PUSH command decreases the Stack Pointer. If software reads the Program Counter

from the Stack after a call or an interrupt, unused bits (15:13) should be masked out.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by one when

data is pushed onto the Stack with the PUSH instruction, and it is decremented by two

when the return address is pushed onto the Stack with subroutine call or interrupt. The

Stack Pointer is incremented by one when data is popped from the Stack with the POP

instruction, and it is incremented by two when data is popped from the Stack with return