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fpga通过vivado实现加法器
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2024-04-16
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fpga通过vivado实现加法器 （138个子文件） 
__synthesis_is_complete__ 0B elaborate.bat 1KB simulate.bat 928B compile.bat 880B runme.bat 229B runme.bat 229B xsim_1.c 5KB ssm.db 538B xsim.dbg 6KB adder_routed.dcp 148KB adder_physopt.dcp 147KB adder_placed.dcp 145KB adder_opt.dcp 10KB adder.dcp 10KB adder.dcp 10KB
xsimk.exe 64KB xsimSettings.ini 1KB xsim.ini 40B vivado_5848.backup.jou 1KB vivado.jou 1002B vivado_3560.backup.jou 1002B vivado_10744.backup.jou 832B vivado.jou 818B vivado.jou 813B ISEWrap.js 8KB ISEWrap.js 8KB rundef.js 1KB rundef.js 1KB vivado_5848.backup.log 58KB runme.log 25KB vivado.log 12KB vivado_3560.backup.log 12KB vivado_10744.backup.log 12KB runme.log 11KB elaborate.log 731B xvlog.log 376B compile.log 376B xsimkernel.log 324B simulate.log 25B xsimcrash.log 0B project_1.lpr 290B xsim.mem 3KB xsim_0.win64.obj 6KB xsim_1.win64.obj 3KB vivado.pb 18KB place_design.pb 13KB route_design.pb 12KB opt_design.pb 10KB init_design.pb 2KB phys_opt_design.pb 2KB xelab.pb 2KB adder_power_summary_routed.pb 723B xvlog.pb 676B adder_utilization_placed.pb 242B adder_utilization_synth.pb 242B vivado.pb 149B adder_timing_summary_routed.pb 52B adder_methodology_drc_routed.pb 52B adder_route_status.pb 43B adder_drc_opted.pb 37B adder_drc_routed.pb 37B adder_bus_skew_routed.pb 30B tb_adder_vlog.prj 285B xsim.reloc 1KB xsim.rlx 733B xil_defaultlib.rlx 427B adder_io_placed.rpt 97KB adder_timing_summary_routed.rpt 21KB adder_utilization_placed.rpt 9KB adder_power_routed.rpt 8KB adder_utilization_synth.rpt 7KB adder_clock_utilization_routed.rpt 6KB adder_drc_routed.rpt 4KB adder_drc_opted.rpt 4KB adder_control_sets_placed.rpt 3KB adder_methodology_drc_routed.rpt 1KB adder_bus_skew_routed.rpt 849B adder_route_status.rpt 588B adder_timing_summary_routed.rpx 16KB adder_power_routed.rpx 9KB adder_drc_routed.rpx 6KB adder_drc_opted.rpx 6KB adder_bus_skew_routed.rpx 1020B adder_methodology_drc_routed.rpx 124B .vivado.begin.rst 220B .vivado.begin.rst 219B .route_design.begin.rst 181B .opt_design.begin.rst 181B .phys_opt_design.begin.rst 181B .place_design.begin.rst 181B .init_design.begin.rst 181B .vivado.end.rst 0B .init_design.end.rst 0B .Vivado_Implementation.queue.rst 0B .route_design.end.rst 0B .phys_opt_design.end.rst 0B .opt_design.end.rst 0B .place_design.end.rst 0B .vivado.end.rst 0B .Vivado_Synthesis.queue.rst 0B共 138 条
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