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TLC5615参考资料PDF
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TLC5615参考资料
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TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142B – OCTOBER 1996 – REVISED MARCH 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
10-Bit CMOS Voltage Output DAC in an
8-Terminal Package
D
5-V Single Supply Operation
D
3-Wire Serial Interface
D
High-Impedance Reference Inputs
D
Voltage Output Range...2 Times the
Reference Input Voltage
D
Internal Power-On Reset
D
Low Power Consumption...1.75 mW Max
D
Update Rate of 1.21 MHz
D
Settling Time to 0.5 LSB...12.5 µs Typ
D
Monotonic Over Temperature
D
Pin Compatible with the Maxim MAX515
applications
D
Battery-Powered Test Instruments
D
Digital Offset and Gain Adjustment
D
Battery Operated/Remote Industrial
Controls
D
Machine and Motion Control Devices
D
Cellular Telephones
description
The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high
impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is
monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is
incorporated to ensure repeatable start-up conditions.
Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to
industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to
produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital
communication protocols include the SPI, QSPI, and Microwire standards.
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operation
from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
†
(D)
PLASTIC DIP
(P)
0°C to 70°C TLC5615CD TLC5615CP
–40°C to 85°C TLC5615ID TLC5615IP
†
Available in tape and reel as the TLC5615CDR and the TLC5615IDR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
1
2
3
4
8
7
6
5
DIN
SCLK
CS
DOUT
V
DD
OUT
REFIN
AGND
D OR P PACKAGE
(TOP VIEW)
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142B – OCTOBER 1996 – REVISED MARCH 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
_
+
DAC
10-Bit DAC Register
Power-ON
Reset
Control
Logic
16-Bit Shift Register
4
Dummy
Bits
2
0s
10 Data Bits
(LSB) (MSB)
REFIN
AGND
CS
SCLK
DIN
OUT
(Voltage Output)
_
+
DOUT
RR
2
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
DIN 1 I Serial data input
SCLK 2 I Serial clock input
CS 3 I Chip select, active low
DOUT 4 O Serial data output for daisy chaining
AGND 5 Analog ground
REFIN 6 I Reference input
OUT 7 O DAC analog voltage output
V
DD
8 Positive power supply
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage (V
DD
to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range to AGND – 0.3 V to V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range to AGND – 0.3 V to V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage at OUT from external source V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current at any terminal ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TLC5615C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC5615I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142B – OCTOBER 1996 – REVISED MARCH 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
DD
4.5 5 5.5 V
High-level digital input voltage, V
IH
2.4 V
Low-level digital input voltage, V
IL
0.8 V
Reference voltage, V
ref
to REFIN terminal 2 2.048 V
DD
–2 V
Load resistance, R
L
2 kΩ
Operating free-air temperature T
A
TLC5615C 0 70 °C
O
pera
ti
ng
f
ree-a
i
r
t
empera
t
ure,
T
A
TLC5615I –40 85 °C
electrical characteristics over recommended operating free-air temperature range, V
DD
= 5 V ± 5%,
V
ref
= 2.048 V (unless otherwise noted)
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 bits
Integral nonlinearity, end point adjusted (INL) V
ref
= 2.048 V, See Note 1 ±1 LSB
Differential nonlinearity (DNL) V
ref
= 2.048 V, See Note 2 ±0.1 ± 0.5 LSB
E
ZS
Zero-scale error (offset error at zero scale) V
ref
= 2.048 V, See Note 3 ±3 LSB
Zero-scale-error temperature coefficient V
ref
= 2.048 V, See Note 4 3 ppm/°C
E
G
Gain error V
ref
= 2.048 V, See Note 5 ±3 LSB
Gain-error temperature coefficient V
ref
= 2.048 V, See Note 6 1 ppm/°C
PSRR
Power-supply rejection ratio
Zero scale
See Notes 7 and 8
80
dB
PSRR
P
ower-supp
l
y re
j
ec
ti
on ra
ti
o
Gain
S
ee
N
o
t
es
7
an
d
8
80
dB
Analog full scale output R
L
= 100 kΩ 2V
ref
(1023/1024) V
NOTES: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).
2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).
4. Zero-scale-error temperature coefficient is given by: E
ZS
TC = [E
ZS
(T
max
) – E
ZS
(T
min
)]/V
ref
× 10
6
/(T
max
– T
min
).
5. Gain error is the deviation from the ideal output (V
ref
– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-scale
error.
6. Gain temperature coefficient is given by: E
G
TC = [E
G
(T
max
) – E
G
(T
min
)]/V
ref
× 10
6
/(T
max
– T
min
).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the V
DD
from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the V
DD
from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero-scale change.
voltage output (OUT)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
Voltage output range R
L
= 10 kΩ 0 V
DD
–0.4 V
Output load regulation accuracy V
O(OUT)
= 2 V, R
L
= 2 kΩ 0.5 LSB
I
OSC
Output short circuit current OUT to V
DD
or AGND 20 mA
V
OL(low)
Output voltage, low-level I
O(OUT)
≤ 5 mA 0.25 V
V
OH(high)
Output voltage, high-level I
O(OUT)
≤ –5 mA 4.75 V
TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142B – OCTOBER 1996 – REVISED MARCH 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
reference input (REFIN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I
Input voltage 0 V
DD
–2 V
r
i
Input resistance 10 MΩ
C
i
Input capacitance 5 pF
digital inputs (DIN, SCLK, CS)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IH
High-level digital input voltage 2.4 V
V
IL
Low-level digital input voltage 0.8 V
I
IH
High-level digital input current V
I
= V
DD
±1 µA
I
IL
Low-level digital input current V
I
= 0 ±1 µA
C
i
Input capacitance 8 pF
digital output (DOUT)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
Output voltage, high-level I
O
= –2 mA V
DD
–1 V
V
OL
Output voltage, low-level I
O
= 2 mA 0.4 V
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX
UNIT
V
DD
Supply voltage 4.5 5 5.5 V
I
DD
Power supply current
V
DD
= 5.5 V,
No load,
All inputs = 0 V or V
DD
V
ref
= 0 150 250 µA
I
DD
P
ower supp
l
y curren
t
V
DD
= 5.5 V,
No load,
All inputs = 0 V or V
DD
V
ref
= 2.048 V 230 350 µA
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Signal-to-noise + distortion, S/(N+D)
V
ref
= 1 V
pp
at 1 kHz + 2.048 Vdc,
code = 11 1111 1111,
See Note 9
60 dB
NOTE 9: The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.
digital input timing requirements (see Figure 1)
PARAMETER MIN NOM MAX UNIT
t
su(DS)
Setup time, DIN before SCLK high 45 ns
t
h(DH)
Hold time, DIN valid after SCLK high 0 ns
t
su(CSS)
Setup time, CS low to SCLK high 1 ns
t
su(CS1)
Setup time, CS high to SCLK high 50 ns
t
h(CSH0)
Hold time, SCLK low to CS low 1 ns
t
h(CSH1)
Hold time, SCLK low to CS high 0 ns
t
w(CS)
Pulse duration, minimum chip select pulse width high 20 ns
t
w(CL)
Pulse duration, SCLK low 25 ns
t
w(CH)
Pulse duration, SCLK high 25 ns
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