System Management Bus (SMBus) Specification Version 3.0
This specification is provided “as is” with no warranties whatsoever, whether express, implied or
statutory, including but not limited to any warranty of merchantability, non-infringement or fitness
for any particular purpose, or any warranty otherwise arising out of any proposal, specification
or sample.
In no event will any specification co-owner be liable to any other party for any loss of profits,
loss of use, incidental, consequential, indirect or special damages arising out of this
specification, whether or not such party had advance notice of the possibility of such damages.
Further, no warranty or representation is made or implied relative to freedom from infringement
of any third party patents when practicing the specification.
Other product and corporate names may be trademarks of other companies and are used only
for explanation and to the owner’s benefit, without intent to infringe.
Revision No.
Date
Notes
Editor
1.0
2/15/95
General Release
Unknown
1.1
12/11/98
Version 1.1 Release
Unknown
2.0
8/3/00
Version 2.0 Release
Unknown
3.0
20 Dec 2014
Version 3.0 Release
Robert V. White
Embedded Power Labs
Questions and comments regarding this
specification may be forwarded to:
techquestions@smiforum.org
For additional information on Smart Battery System
Specifications, visit the SBS Implementer’s Forum
(SBS-IF) at:
www.sbs-forum.org
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System Management Bus (SMBus) Specification Version 3.0
Table of Contents
1. Introduction ............................................................................................................................................. 8
1.1 Overview .................................................................................................................................... 8
1.2 Audience .................................................................................................................................... 8
1.3 Scope ......................................................................................................................................... 8
1.4 Organization of this document ................................................................................................... 8
2. Related Documents And Reference Information .................................................................................... 9
2.1 Scope ......................................................................................................................................... 9
2.2 Applicable Documents ............................................................................................................... 9
2.3 Reference Documents ............................................................................................................... 9
2.4 Definitions Of Terms ................................................................................................................ 10
2.5 Conventions ............................................................................................................................. 11
2.5.1 Numeric formats ...................................................................................................... 11
2.5.2 SMBus addresses ................................................................................................... 12
2.5.3 Transaction protocol diagrams ................................................................................ 12
3. General Characteristics ........................................................................................................................ 14
4. Layer 1 – The Physical Layer ............................................................................................................... 15
4.1 Electrical Characteristics Of SMBus Devices – Two Discrete Worlds .................................... 15
4.2 SMBus Common AC specifications ......................................................................................... 16
4.2.1 General timing conditions ........................................................................................ 21
4.2.2 Device timeout definitions and conditions ............................................................... 21
4.2.3 Master device clock extension definitions and conditions....................................... 21
4.2.4 Slave device clock extension .................................................................................. 22
4.2.5 SMBDAT low timeout .............................................................................................. 22
4.3 DC Specifications .................................................................................................................... 22
4.3.1 Supply voltage requirements ................................................................................... 23
4.3.2 SMBus branch circuit model ................................................................................... 23
4.3.3 Low Power DC parameters ........................................................................................ 24
4.3.4 High Power DC specifications ................................................................................. 25
4.3.5 Additional common Low and High Power specifications ......................................... 27
5. Layer 2 – The Data Link Layer ............................................................................................................. 28
5.1 Bit Transfers ............................................................................................................................ 28
5.1.1 Data validity ............................................................................................................. 28
5.1.2 START and STOP conditions ................................................................................. 28
5.1.3 Bus idle condition .................................................................................................... 29
5.2 Data Transfers On SMBus ...................................................................................................... 29
5.3 Clock Generation And Arbitration ............................................................................................ 30
5.3.1 Synchronization ....................................................................................................... 30
5.3.2 Arbitration ................................................................................................................ 31
5.3.3 Clock low extending ................................................................................................ 32
5.4 Data Transfer Formats ............................................................................................................ 34
6. Layer 3 – Network layer ........................................................................................................................ 34
6.1 Usage Model............................................................................................................................ 34
6.1.1 Master devices ........................................................................................................ 34
6.1.2 Slave devices .......................................................................................................... 35
6.1.3 Host ......................................................................................................................... 35
6.2 Device Identification – Slave Address ..................................................................................... 35
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System Management Bus (SMBus) Specification Version 3.0
6.2.1 Uniqueness required ............................................................................................... 35
6.2.2 SMBus address types ............................................................................................. 35
6.3 Using A Device ........................................................................................................................ 37
6.4 Packet Error Checking ............................................................................................................. 37
6.4.1 Packet error checking implementation .................................................................... 37
6.5 Bus Protocols........................................................................................................................... 39
6.5.1 Quick Command ...................................................................................................... 39
6.5.2 Send Byte ................................................................................................................ 39
6.5.3 Receive Byte ........................................................................................................... 40
6.5.4 Write Byte/Word ...................................................................................................... 40
6.5.5 Read Byte/Word ...................................................................................................... 41
6.5.6 Process Call ............................................................................................................ 42
6.5.7 Block Write/Read ..................................................................................................... 42
6.5.8 Block Write-Block Read Process Call ..................................................................... 43
6.5.9 SMBus Host Notify protocol .................................................................................... 44
6.5.10 Write 32 protocol ..................................................................................................... 45
6.5.11 Read 32 protocol ..................................................................................................... 46
6.5.12 Write 64 protocol ..................................................................................................... 46
6.5.13 Read 64 protocol ..................................................................................................... 47
6.6 SMBus Address Resolution Protocol ...................................................................................... 48
6.6.1 Unique Device Identifier (UDID) .............................................................................. 49
6.6.2 Power-on reset ........................................................................................................ 53
6.6.3 ARP commands ...................................................................................................... 53
Appendix A. Optional SMBus signals ......................................................................................................... 72
A.1 SMBSUS# ................................................................................................................................ 72
A.2 SMBALERT# ........................................................................................................................... 73
Appendix B. Differences between SMBus and I
2
C
................................................................................. 75
B.1 V
DD
And Threshold Voltage Differences .................................................................................. 75
B.2 Minimum Bus Speed And Maximum Clock Stretching ............................................................ 75
B.3 Address Acknowledge ............................................................................................................. 75
B.4 SMBus Protocols ..................................................................................................................... 76
B.5 REPEATED START Condition ................................................................................................ 76
B.6 SMBus Low Power Version ..................................................................................................... 76
B.7 Tables Of Differences .............................................................................................................. 76
Appendix C. SMBus Device Address Assignments .................................................................................... 81
Appendix D. Changes This Revision .......................................................................................................... 83
D.1 Maximum Bus Frequency ........................................................................................................ 83
D.2 Electrical Drive Levels ............................................................................................................. 83
D.3 Data Hold Time ........................................................................................................................ 83
D.4 T
SPIKE
In Place Of V
NOISE
.......................................................................................................... 85
D.5 Zone Read And Write Protocols .............................................................................................. 85
D.6 255 Bytes in Process Call ........................................................................................................ 85
D.7 32 And 64 Bit Protocols ........................................................................................................... 85
D.8 Reformatting Of Text, Figures, And Tables ............................................................................. 85
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System Management Bus (SMBus) Specification Version 3.0
Table of Tables
Table 1. Transaction protocol diagram symbols and elements .................................................................. 12
Table 2. SMBus AC specifications .............................................................................................................. 18
Table 3. Low Power SMBus DC specification ............................................................................................. 24
Table 4. High Power SMBus DC specification ............................................................................................ 26
Table 5: UDID bit fields descriptions ........................................................................................................... 49
Table 6: 8-bit device capabilities field descriptions ..................................................................................... 50
Table 7: Version/Revision bit fields description .......................................................................................... 50
Table 8: Interface field bit fields description ................................................................................................ 51
Table 9. Internal state of ARP-capable devices on Power-On Reset ......................................................... 53
Table 10. ARP command number scheme ................................................................................................. 54
Table 11. SMBus device characterizations ................................................................................................. 54
Table 12. Device decodes of AV and AR flags ........................................................................................... 66
Table 13.
SMBus Suspend parameters ...................................................................................................... 72
Table 14. Selected parameter differences between Standard-Mode I²C and 100 kHz Class SMBus ....... 76
Table 15. DC parameter differences between Fast-mode I²C and 400 kHz Class SMBus
................. 77
Table 16. DC parameter differences between Fast-mode Plus I²C and 1 MHz Class SMBus
........... 78
Table 17. Reserved and pre-assigned SMBus addresses ......................................................................... 81
Table of Figures
Figure 1: Generic transaction diagram ........................................................................................................ 14
Figure 2: SMBus Topology .......................................................................................................................... 15
Figure 3: SMBus pull-up circuitry ................................................................................................................ 15
Figure 4: Example input and output stages of SMBus devices .................................................................. 16
Figure 5. SMBus timing measurements ...................................................................................................... 18
Figure 6. Timeout intervals .......................................................................................................................... 21
Figure 7: Clock extension measurement intervals ...................................................................................... 22
Figure 8:
SMBus branch with multiple devices attached
......................................................................... 23
Figure 9:
SMBus circuit model
.................................................................................................................. 24
Figure 10: Data validity ............................................................................................................................... 28
Figure 11: START and STOP conditions .................................................................................................... 28
Figure 12: SMBus byte format .................................................................................................................... 29
Figure 13:
ACK signaling of SMBus
.......................................................................................................... 29
Figure 14. NACK signaling on SMBus ........................................................................................................ 30
Figure 15: SMBus clock synchronization .................................................................................................... 31
Figure 16: SMBus arbitration
.................................................................................................................... 32
Figure 17: Periodic clock stretching by a slave SMBus device
.............................................................. 33
Figure 18: Random clock stretching
......................................................................................................... 34
Figure 19: Data transfer over SMBus
...................................................................................................... 34
Figure 20: Quick Command protocol
....................................................................................................... 39
Figure 21: Send Byte protocol
.................................................................................................................. 40
Figure 22: Send Byte protocol with PEC ..................................................................................................... 40
Figure 23: Receive Byte protocol
............................................................................................................. 40
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