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###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 4.0
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh File :
a) The "vcs_run.sh" file contains the commands for simulation of hdl files.
b) Libraries must be mapped before running simulations. Following
procedu
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FPGA通过EMAC实现ARP通信 (2846个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
assumedExternalFilesCache 4B
xsim.ini.bak 26KB
AXIAttachTOE.v.bak 11KB
toe_top.v.bak 9KB
xsim_run.bat 3KB
elaborate.bat 1KB
compile.bat 988B
simulate.bat 912B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
C21017_TOP.bit 8.41MB
C21017_TOP.bit 8.39MB
C21017_TOP.bit 8.35MB
C21017_TOP.bit 8.33MB
C21017_TOP.bit 8.32MB
C21017_TOP.bit 8.3MB
C21017_TOP.bit 8.3MB
C21017_TOP.bit 8.29MB
C21017_TOP.bit 8.28MB
C21017_TOP.bit 8.27MB
C21017_TOP.bit 8.24MB
C21017_TOP.bit 8.23MB
C21017_TOP.bit 8.21MB
C21017_TOP.bit 8.2MB
C21017_TOP.bit 8.19MB
C21017_TOP.bit 8.16MB
C21017_TOP.bit 8.15MB
C21017_TOP.bit 8.05MB
C21017_TOP.bit 7.83MB
C21017_TOP.bit 7.54MB
C21017_TOP.bit 7.14MB
C21017_TOP.bit 7.02MB
C21017_TOP.bit 6.79MB
C21017_TOP.bit 6.64MB
C21017_TOP.bit 6.53MB
C21017_TOP.bit 5.77MB
EMAC_TOP.bit 1.81MB
xsim_3.c 165KB
specs.c 1B
specs.cpp 1B
variablesAndContainers.dat 96B
xsim.dbg 56KB
EMAC_TOP_routed.dcp 5.09MB
EMAC_TOP_placed.dcp 4.35MB
mig_7series_0.dcp 3.86MB
EMAC_TOP_opt.dcp 2.81MB
ila_rx.dcp 1.17MB
ila_rx.dcp 1.17MB
ila_rx.dcp 1.16MB
ila_rx.dcp 1.14MB
ila_usb_cmdfifo.dcp 986KB
ila_usb_cmd.dcp 888KB
ila_usb.dcp 854KB
ila_tx.dcp 853KB
ila_tx.dcp 853KB
ila_tx.dcp 851KB
ila_tx.dcp 850KB
ila_rx.dcp 795KB
ila_gtx_cmd.dcp 764KB
ila_usb_bus.dcp 757KB
ila_usb_bus.dcp 753KB
ddrfifo_rdwr_ctrl_ila.dcp 680KB
ila_rx.dcp 634KB
ila_tx.dcp 615KB
ila_rx.dcp 585KB
ila_rx.dcp 569KB
EMAC1G.dcp 359KB
EMAC1G.dcp 359KB
XilEMAC.dcp 358KB
XilEMAC.dcp 358KB
dbg_hub.dcp 358KB
EMAC1G.dcp 358KB
dbg_hub.dcp 348KB
fifo_toe2ddr.dcp 137KB
fifo_ddr2toe_64_32.dcp 134KB
FIFO_EMAC.dcp 123KB
PS2toe_FIFO.dcp 121KB
EMAC_TOP.dcp 113KB
FIFO2kx9.dcp 85KB
clk_pll.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_ETH.dcp 10KB
clk_wiz_ETH.dcp 10KB
clk_wiz_ETH.dcp 10KB
sim.do 7KB
compile.do 3KB
compile.do 3KB
compile.do 2KB
compile.do 2KB
compile.do 1KB
compile.do 1KB
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