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UNH–IOL
NVMe Testing Service
Test Plan for NVMe PCIe Transport Conformance
Version 19.0
Target Specification: NVMe over PCIe Transport
Specification 1.0a
Technical Document
Last Updated: January 04, 2023
UNH–IOL NVMe Testing Service
21 Madbury Rd Suite 100
Durham, NH 03824
Tel: +1 603–862–0090
Fax: +1 603–862–4181
Email: nvmelab@iol.unh.edu
University of New Hampshire InterOperability Laboratory – NVMe PCIe Transport Conformance Test Suite
UNH–IOL NVMe Testing Service 2 NVMe PCIe Transport Conformance Test Suite
© 2023 UNH–IOL
TABLE OF CONTENTS
TABLE OF CONTENTS ..................................................................................................................... 2
MODIFICATION RECORD ................................................................................................................ 3
ACKNOWLEDGMENTS ..................................................................................................................... 3
INTRODUCTION ............................................................................................................................... 4
REFERENCES ................................................................................................................................... 6
ABBREVIATIONS ............................................................................................................................. 7
Group 1: Controller Architecture (PCIeC Group 6) ............................................................. 8
Test 1.1 – Controller Level Reset – Conventional Reset (M) (PCIeC 6.1) ..................................... 9
Test 1.2 – Controller Level Reset – Function Level Reset (M) (PCIeC 6.2) ................................ 10
Test 1.3 – Controller Level Reset – NVM Subsystem Reset (M) (PCIeC 6.4) ............................. 11
Group 2: Power State Transitions ......................................................................................... 13
Test 2.1 – Autonomous Power State Transitions Enabled (M) (PCIeC 8.1) ................................ 14
Test 2.2 – Return from Non–Operational State (FYI) (PCIeC 8.2) .............................................. 15
Case 1: Basic Operation (M) (PCIeC 8.2.1) ................................................................................................. 15
Case 2: Non-Operation State Admin Commands (M) (PCIeC 8.2.2) ........................................................... 15
Test 2.3 – Autonomous Power State Transition (M) (PCIeC 8.3) ................................................ 17
Case 1: Proper Structure ............................................................................................................................... 17
Test 2.4 – Power State Entrance Latency (M) (PCIeC 8.4) ........................................................... 18
Test 2.5 – Power State Exit Latency (M) (PCIeC 8.5) ................................................................... 19
Test 2.6 – Relative Read Throughput (M) (PCIeC 8.6) ................................................................. 20
Test 2.7 – Relative Write Throughput (M) (PCIeC 8.7) ................................................................ 21
Test 2.8 – Host Controlled Thermal Management (M) (PCIeC 8.8) ............................................ 22
Case 1: Basic Operation (M) ........................................................................................................................ 22
Case 2: Invalid Field (M) .............................................................................................................................. 22
Group 3: System Bus Registers (PCIeC Group 10).............................................................. 24
Test 3.1 – PCI Express Capability Registers (M) (PCIeC 10.1).................................................... 25
Appendix A: DEFAULT TEST SETUP ........................................................................................... 26
Appendix B: NOTES ON TEST PROCEDURES .............................................................................. 27
Appendix C: TEST TOOLS ........................................................................................................... 28
Appendix D: NVME INTEGRATORS LIST REQUIREMENTS ....................................................... 29
University of New Hampshire InterOperability Laboratory – NVMe PCIe Transport Conformance Test Suite
UNH–IOL NVMe Testing Service 3 NVMe PCIe Transport Conformance Test Suite
© 2023 UNH–IOL
MODIFICATION RECORD
2022 January 21 (Version 1.0) Initial Release
Tim Sheehan:
1. Initial release of the NVMe PCIe Transport Conformance Test Suite v17, inclusive of PCIe tests
from the NVMe Conformance Test Suite v16.0
2022 July 14 (Version 18.0) Final Release
Tim Sheehan:
1. Program Revision Update
2023 January 04 (Version 19.0) Final Release
Tim Sheehan:
Tests with Status Changes
1. Test 2.2.1 updated from (FYI) to (M)
2. Test 2.2.2 updated from (FYI) to (M)
ACKNOWLEDGMENTS
The UNH–IOL would like to acknowledge the efforts of the following individuals in the development of this test
plan:
Tim Sheehan UNH InterOperability Laboratory
University of New Hampshire InterOperability Laboratory – NVMe PCIe Transport Conformance Test Suite
UNH–IOL NVMe Testing Service 4 NVMe PCIe Transport Conformance Test Suite
© 2023 UNH–IOL
INTRODUCTION
The University of New Hampshire’s InterOperability Laboratory (IOL) is an institution designed to improve the
interoperability of standards–based products by providing a neutral environment where a product can be tested against
other implementations of a common standard, both in terms of interoperability and conformance. This particular suite
of tests has been developed to help implementers evaluate the NVMe functionality of their products. This test suite is
aimed at validating products in support of the work being directed by the NVMe Promoters Group.
These tests are designed to determine if a product conforms to specifications defined in the NVM Express PCIe
Transport Specification Revision 1.0 specification and NVM Express Base Specification 2.0a. Successful completion
of these tests provide a reasonable level of confidence that the Device Under Test (DUT) will function properly in
many NVMe environments. Transport testing should also include those tests for tests in respective I/O command set
test plans
The tests contained in this document are organized in order to simplify the identification of information related to a
test, and to facilitate in the actual testing process. Tests are separated into groups, primarily in order to reduce setup
time in the lab environment, however the different groups typically also tend to focus on specific aspects of device
functionality. A two–number, dot–notated naming system is used to catalog the tests. This format allows for the
addition of future tests in the appropriate groups without requiring the renumbering of the subsequent tests. The NVMe
2.0 refactoring effort has made it important to reference pre-2.0 test cases that have moved to a 2.0 refactored test
plan. This new test case numbers will be realized at the end of each test case name with the legacy test case number
noted.
The test definitions themselves are intended to provide a high–level description of the motivation, resources,
procedures, and methodologies specific to each test. Formally, each test description contains the following sections:
Purpose
The purpose is a brief statement outlining what the test attempts to achieve. The test is written at the functional level.
References
This section specifies all reference material external to the test suite, including the specific references for the test in
question, and any other references that might be helpful in understanding the test methodology and/or test results.
External sources are always referenced by a bracketed number (e.g., [1]) when mentioned in the test description. Any
other references in the test description that are not indicated in this manner refer to elements within the test suite
document itself (e.g., “Appendix 5.A”, or “Table 5.1.1–1”).
Resource Requirements
The requirements section specifies the test hardware and/or software needed to perform the test. This is generally
expressed in terms of minimum requirements, however in some cases specific equipment manufacturer/model
information may be provided.
Last Modification
This specifies the date of the last modification to this test.
Discussion
The discussion covers the assumptions made in the design or implementation of the test, as well as known limitations.
Other items specific to the test are covered here as well.
Test Setup
The setup section describes the initial configuration of the test environment. Small changes in the configuration should
not be included here, and are generally covered in the test procedure section (next).
Procedure
University of New Hampshire InterOperability Laboratory – NVMe PCIe Transport Conformance Test Suite
UNH–IOL NVMe Testing Service 5 NVMe PCIe Transport Conformance Test Suite
© 2023 UNH–IOL
The procedure section of the test description contains the systematic instructions for carrying out the test. It provides
a cookbook approach to testing, and may be interspersed with observable results. These procedures should be the ideal
test methodology, independent of specific tool limitations or restrictions.
Observable Results
This section lists the specific observable items that can be examined by the tester in order to verify that the DUT is
operating properly. When multiple values for an observable are possible, this section provides a short discussion on
how to interpret them. The determination of a pass or fail outcome for a particular test is generally based on the
successful (or unsuccessful) detection of a specific observable.
Possible Problems
This section contains a description of known issues with the test procedure, which may affect test results in certain
situations. It may also refer the reader to test suite appendices and/or other external sources that may provide more
detail regarding these issues.
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