Linux5.10内核：linux-dovetail-v5.10.76-dovetail3.tar.gz

// SPDX-License-Identifier: ISC /* * Copyright (c) 2010 Broadcom Corporation */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include <linux/kernel.h> #include <linux/delay.h> #include <linux/cordic.h> #include <brcm_hw_ids.h> #include <aiutils.h> #include <chipcommon.h> #include <pmu.h> #include <d11.h> #include <phy_shim.h> #include "phy_int.h" #include "phy_hal.h" #include "phy_radio.h" #include "phyreg_n.h" #include "phytbl_n.h" #include "soc.h" #define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \ read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \ ((core == PHY_CORE_0) ? \ radio_type##_##jspace##0 : \ radio_type##_##jspace##1)) #define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \ write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \ ((core == PHY_CORE_0) ? \ radio_type##_##jspace##0 : \ radio_type##_##jspace##1), value) #define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \ write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value) #define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \ read_radio_reg(pi, ((core == PHY_CORE_0) ? \ radio_type##_##jspace##0##_##reg_name : \ radio_type##_##jspace##1##_##reg_name)) #define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \ write_radio_reg(pi, ((core == PHY_CORE_0) ? \ radio_type##_##jspace##0##_##reg_name : \ radio_type##_##jspace##1##_##reg_name), \ value) #define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \ read_radio_reg(pi, ((core == PHY_CORE_0) ? \ radio_type##_##reg_name##_##jspace##0 : \ radio_type##_##reg_name##_##jspace##1)) #define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \ write_radio_reg(pi, ((core == PHY_CORE_0) ? \ radio_type##_##reg_name##_##jspace##0 : \ radio_type##_##reg_name##_##jspace##1), \ value) #define NPHY_ACI_MAX_UNDETECT_WINDOW_SZ 40 #define NPHY_ACI_CHANNEL_DELTA 5 #define NPHY_ACI_CHANNEL_SKIP 4 #define NPHY_ACI_40MHZ_CHANNEL_DELTA 6 #define NPHY_ACI_40MHZ_CHANNEL_SKIP 5 #define NPHY_ACI_40MHZ_CHANNEL_DELTA_GE_REV3 6 #define NPHY_ACI_40MHZ_CHANNEL_SKIP_GE_REV3 5 #define NPHY_ACI_CHANNEL_DELTA_GE_REV3 4 #define NPHY_ACI_CHANNEL_SKIP_GE_REV3 3 #define NPHY_NOISE_NOASSOC_GLITCH_TH_UP 2 #define NPHY_NOISE_NOASSOC_GLITCH_TH_DN 8 #define NPHY_NOISE_ASSOC_GLITCH_TH_UP 2 #define NPHY_NOISE_ASSOC_GLITCH_TH_DN 8 #define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_UP 2 #define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_DN 8 #define NPHY_NOISE_NOASSOC_ENTER_TH 400 #define NPHY_NOISE_ASSOC_ENTER_TH 400 #define NPHY_NOISE_ASSOC_RX_GLITCH_BADPLCP_ENTER_TH 400 #define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX 44 #define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX_REV_7 56 #define NPHY_NOISE_NOASSOC_CRSIDX_INCR 16 #define NPHY_NOISE_ASSOC_CRSIDX_INCR 8 #define NPHY_IS_SROM_REINTERPRET NREV_GE(pi->pubpi.phy_rev, 5) #define NPHY_RSSICAL_MAXREAD 31 #define NPHY_RSSICAL_NPOLL 8 #define NPHY_RSSICAL_MAXD (1<<20) #define NPHY_MIN_RXIQ_PWR 2 #define NPHY_RSSICAL_W1_TARGET 25 #define NPHY_RSSICAL_W2_TARGET NPHY_RSSICAL_W1_TARGET #define NPHY_RSSICAL_NB_TARGET 0 #define NPHY_RSSICAL_W1_TARGET_REV3 29 #define NPHY_RSSICAL_W2_TARGET_REV3 NPHY_RSSICAL_W1_TARGET_REV3 #define NPHY_CALSANITY_RSSI_NB_MAX_POS 9 #define NPHY_CALSANITY_RSSI_NB_MAX_NEG -9 #define NPHY_CALSANITY_RSSI_W1_MAX_POS 12 #define NPHY_CALSANITY_RSSI_W1_MAX_NEG (NPHY_RSSICAL_W1_TARGET - \ NPHY_RSSICAL_MAXREAD) #define NPHY_CALSANITY_RSSI_W2_MAX_POS NPHY_CALSANITY_RSSI_W1_MAX_POS #define NPHY_CALSANITY_RSSI_W2_MAX_NEG (NPHY_RSSICAL_W2_TARGET - \ NPHY_RSSICAL_MAXREAD) #define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f))) #define NPHY_RSSI_NB_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_NB_MAX_POS) || \ ((x) < NPHY_CALSANITY_RSSI_NB_MAX_NEG)) #define NPHY_RSSI_W1_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W1_MAX_POS) || \ ((x) < NPHY_CALSANITY_RSSI_W1_MAX_NEG)) #define NPHY_RSSI_W2_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W2_MAX_POS) || \ ((x) < NPHY_CALSANITY_RSSI_W2_MAX_NEG)) #define NPHY_IQCAL_NUMGAINS 9 #define NPHY_N_GCTL 0x66 #define NPHY_PAPD_EPS_TBL_SIZE 64 #define NPHY_PAPD_SCL_TBL_SIZE 64 #define NPHY_NUM_DIG_FILT_COEFFS 15 #define NPHY_PAPD_COMP_OFF 0 #define NPHY_PAPD_COMP_ON 1 #define NPHY_SROM_TEMPSHIFT 32 #define NPHY_SROM_MAXTEMPOFFSET 16 #define NPHY_SROM_MINTEMPOFFSET -16 #define NPHY_CAL_MAXTEMPDELTA 64 #define NPHY_NOISEVAR_TBLLEN40 256 #define NPHY_NOISEVAR_TBLLEN20 128 #define NPHY_ANARXLPFBW_REDUCTIONFACT 7 #define NPHY_ADJUSTED_MINCRSPOWER 0x1e /* 5357 Chip specific ChipControl register bits */ #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ #define NPHY_CAL_TSSISAMPS 64 #define NPHY_TEST_TONE_FREQ_40MHz 4000 #define NPHY_TEST_TONE_FREQ_20MHz 2500 #define MAX_205x_RCAL_WAITLOOPS 10000 #define NPHY_RXCAL_TONEAMP 181 #define NPHY_RXCAL_TONEFREQ_40MHz 4000 #define NPHY_RXCAL_TONEFREQ_20MHz 2000 #define TXFILT_SHAPING_OFDM20 0 #define TXFILT_SHAPING_OFDM40 1 #define TXFILT_SHAPING_CCK 2 #define TXFILT_DEFAULT_OFDM20 3 #define TXFILT_DEFAULT_OFDM40 4 struct nphy_iqcal_params { u16 txlpf; u16 txgm; u16 pga; u16 pad; u16 ipa; u16 cal_gain; u16 ncorr[5]; }; struct nphy_txiqcal_ladder { u8 percent; u8 g_env; }; struct nphy_ipa_txcalgains { struct nphy_txgains gains; bool useindex; u8 index; }; struct nphy_papd_restore_state { u16 fbmix[2]; u16 vga_master[2]; u16 intpa_master[2]; u16 afectrl[2]; u16 afeoverride[2]; u16 pwrup[2]; u16 atten[2]; u16 mm; }; struct nphy_ipa_txrxgain { u16 hpvga; u16 lpf_biq1; u16 lpf_biq0; u16 lna2; u16 lna1; s8 txpwrindex; }; #define NPHY_IPA_RXCAL_MAXGAININDEX (6 - 1) static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_5GHz[] = { {0, 0, 0, 0, 0, 100}, {0, 0, 0, 0, 0, 50}, {0, 0, 0, 0, 0, -1}, {0, 0, 0, 3, 0, -1}, {0, 0, 3, 3, 0, -1}, {0, 2, 3, 3, 0, -1} }; static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_2GHz[] = { {0, 0, 0, 0, 0, 128}, {0, 0, 0, 0, 0, 70}, {0, 0, 0, 0, 0, 20}, {0, 0, 0, 3, 0, 20}, {0, 0, 3, 3, 0, 20}, {0, 2, 3, 3, 0, 20} }; static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_5GHz_rev7[] = { {0, 0, 0, 0, 0, 100}, {0, 0, 0, 0, 0, 50}, {0, 0, 0, 0, 0, -1}, {0, 0, 0, 3, 0, -1}, {0, 0, 3, 3, 0, -1}, {0, 0, 5, 3, 0, -1} }; static const struct nphy_ipa_txrxgain nphy_ipa_rxcal_gaintbl_2GHz_rev7[] = { {0, 0, 0, 0, 0, 10}, {0, 0, 0, 1, 0, 10}, {0, 0, 1, 2, 0, 10}, {0, 0, 1, 3, 0, 10}, {0, 0, 4, 3, 0, 10}, {0, 0, 6, 3, 0, 10} }; enum { NPHY_RXCAL_GAIN_INIT = 0, NPHY_RXCAL_GAIN_UP, NPHY_RXCAL_GAIN_DOWN }; #define wlc_phy_get_papd_nphy(pi) \ (read_phy_reg((pi), 0x1e7) & \ ((0x1 << 15) | \ (0x1 << 14) | \ (0x1 << 13))) static const u16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = { {-377, 137, -407, 208, -1527, 956, 93, 186, 93, 230, -44, 230, 201, -191, 201}, {-77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5, 26, 34, -32, 34}, {-360, 164, -376, 164, -1533, 576, 308, -314, 308, 121, -73, 121, 91, 124, 91}, {-295, 200, -363, 142, -1391, 826, 151, 301, 151, 151, 301, 151, 602, -752, 602}, {-92, 58, -96, 49, -104, 44, 17, 35, 17, 12, 25, 12, 13, 27, 13}, {-375, 136, -399, 209, -1479, 949, 130, 260, 130, 230, -44, 230, 201, -191, 201}, {0xed9, 0xc8, 0xe95, 0x8e, 0xa91, 0x33a, 0x97, 0x12d, 0x97, 0x97, 0x12d, 0x97, 0x25a, 0xd10, 0x25a} }; struct chan_info_nphy_2055 { u16 chan; u16 freq; uint unknown; u8 RF_pll_ref; u8 RF_rf_pll_mod1; u8 RF_rf_pll_mod0; u8 RF_vco_cap_tail; u8 RF_vco_cal1; u8 RF_vco_cal2; u8 RF_pll_lf_c1; u8 RF_pll_lf_r1; u8 RF_pll_lf_c2; u8 RF_lgbuf_cen_buf; u8 RF_lgen_tune1; u8 RF_lgen_tune2; u8 RF_core1_lgbuf_a_tune; u8 RF_core1_lgbuf_g_tune; u8 RF_core1_rxrf_reg1; u8 RF_core1_tx_pga_pad_tn; u8 RF_core1_tx_mx_