################################################################################
# Vivado (TM) v2017.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
(详细项目内容请看对应博客正文,本资源为对应项目工程,含仿真文件) 一、项目要求 1.输入报文长度64~2048字节; 2.输入报文之间最小间隔为两拍; 3.输出报文的前两拍添加16bit报文长度信息;第1拍为报文长度高8位;第2拍为报文长度低8位;第3拍开始为输入报文; 二、项目方案 1. 要求输出报文,且报文输出在报文长度输出之后,所以需要先对输入报文进行缓存,根据输入报文的位宽和长度范围,此处选择合适的同步FIFO即可;(如果是IC,那么就需要自己写FIFO,可以参考本博客的FIFO介绍) 这里项目提出了第1个要求,掌握FIFO的使用。 2. 要求输出报文长度,所以需要对输入报文长度进行计数,并将其缓存; 此处有坑,若只用寄存器对长度进行缓存,存在被后续报文长度覆盖的风险,故需要第2个FIFO对报文长度进行缓存。 3. 要求先输出报文长度然后紧跟着输出报文,此处需要对时序进行设计,需要掌握FIFO的读写时序,需要理解fpga的时钟沿采样。 理解:时钟沿采样及数据下一时钟沿变化。
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(精选)FPGA项目沙盘演练-基础版报文收发(vivado2017.4) (292个子文件)
xsim.ini.bak 19KB
compile.bat 996B
elaborate.bat 948B
simulate.bat 804B
runme.bat 229B
xsim_1.c 26KB
xsim_1.c 25KB
xsim.dbg 18KB
xsim.dbg 15KB
sync_fifo_w10_d4096.dcp 89KB
sync_fifo_w10_d4096.dcp 89KB
sync_fifo_w10_d4096.dcp 88KB
sync_fifo_w16_d16.dcp 70KB
sync_fifo_w16_d16.dcp 65KB
sync_fifo_w16_d16.dcp 65KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 1KB
compile.do 981B
compile.do 977B
compile.do 967B
compile.do 963B
simulate.do 362B
simulate.do 362B
simulate.do 357B
simulate.do 356B
simulate.do 356B
simulate.do 353B
elaborate.do 229B
elaborate.do 225B
simulate.do 215B
simulate.do 211B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
xsimk.exe 251KB
xsimk.exe 241KB
run.f 799B
run.f 795B
usage_statistics_ext_xsim.html 3KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
.xsim_webtallk.info 64B
xsim.ini 19KB
xsim.ini 19KB
xsim.ini 19KB
xsimSettings.ini 738B
xsimSettings.ini 738B
webtalk.jou 804B
webtalk_9856.backup.jou 804B
webtalk_11044.backup.jou 799B
webtalk_14780.backup.jou 799B
vivado.jou 767B
ISEWrap.js 7KB
rundef.js 1KB
runme.log 42KB
runme.log 41KB
runme.log 41KB
runme.log 40KB
elaborate.log 1KB
webtalk_9856.backup.log 981B
webtalk.log 981B
webtalk_11044.backup.log 976B
webtalk_14780.backup.log 976B
xvlog.log 740B
compile.log 740B
xsimkernel.log 328B
xsimkernel.log 320B
simulate.log 50B
xsimcrash.log 0B
xsimcrash.log 0B
xvhdl.log 0B
zmj0001.lpr 290B
xsim.mem 57KB
xsim.mem 57KB
xsim_0.win64.obj 219KB
xsim_0.win64.obj 207KB
xsim_1.win64.obj 20KB
xsim_1.win64.obj 19KB
elab.opt 234B
elab.opt 230B
vivado.pb 71KB
vivado.pb 70KB
xelab.pb 3KB
xvlog.pb 1KB
sync_fifo_w10_d4096_utilization_synth.pb 289B
xvhdl.pb 16B
zmj0001_tb_vlog.prj 423B
zmj0001_vlog.prj 386B
vlog.prj 161B
vlog.prj 157B
zmj0001_vhdl.prj 75B
共 292 条
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