DAC0832程序和proteus原理图，程序流程图绘制DAC0832控制时序图（单寄存器）。DAC0832的芯片手册以及

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lst：5个

obj：5个

pdsbak：5个

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嵌入式硬件

DAC0832

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DAC.zip （65个子文件）

DAC

dac0832阶梯波

dac08323.DSN 102KB

Last Loaded dac08323.pdsbak 17KB

Last Loaded dac08323.DBK 102KB

dac08323.pdsprj.DESKTOP-C3MV6OD.86132.workspace 2KB

C语言

jietic 3KB

jietic.plg 181B

jietic.LST 2KB

jietic.__i 64B

jietic.build_log.htm 1001B

jietic.hex 232B

STARTUP.LST 14KB

jietic.uvproj 14KB

jietic.lnp 45B

jietic_uvopt.bak 54KB

jietic.M51 4KB

jietic.uvopt 6KB

jietic.c 946B

jietic.uvgui.86132 89KB

STARTUP.A51 6KB

jietic.OBJ 3KB

STARTUP.OBJ 749B

jietic_uvproj.bak 13KB

汇编

jietihuibian 407B

jieti.LST 2KB

jietihuibian.plg 1KB

jietihuibian_uvproj.bak 0B

jietihuibian.lnp 34B

jietihuibian.hex 114B

jietihuibian.uvopt 54KB

jieti.asm 692B

STARTUP.A51 6KB

jieti.OBJ 364B

jietihuibian.uvproj 13KB

jietihuibian.M51 2KB

dac08323.PWI 766B

DAC8032(1915040546).pdsprj.DESKTOP-C3MV6OD.86132.workspace 1KB

172B3BF5E4B79DF20D797A13FEB48D1C.png 3.39MB

0832电压简单输出

DAC8032(1915040546).pdsprj.DESKTOP-C3MV6OD.86132.workspace 2KB

1915040546.uvproj 14KB

TUBE

TUBE.h 1KB

TUBE.c 2KB

DAC0832简单电压输出设计.docx 663KB

Last Loaded DAC8032(1915040546).pdsbak 21KB

Objects

TUBE.obj 7KB

1915040546.LIB 2KB

1915040546.lnp 114B

1915040546.obj 4KB

1915040546 11KB

1915040546.__b 92B

TUBE.__i 136B

1915040546.build_log.htm 1KB

1915040546.hex 3KB

1915040546.uvgui.86132 175KB

1915040546.c 797B

DAC8032(1915040546).pdsprj 21KB

1915040546.uvopt 6KB

Listings

TUBE.lst 4KB

1915040546.m51 9KB

1915040546.lst 2KB

Backup Of DAC8032(1915040546).pdsbak 21KB

Last Loaded DAC8032(1915040546).pdsbak 17KB

课程设计-基于DAC0832的波形发生器设计.doc 2.67MB

芯片手册.PDF 554KB

DAC0832波形图C语言程序.doc 29KB

Backup Of DAC8032(1915040546).pdsbak 17KB

DAC0830/DAC0832

8-Bit µP Compatible, Double-Buffered D to A Converters

General Description

The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying

DAC designed to interface directly with the 8080, 8048,

8085, Z80

, and other popular microprocessors. A deposited

silicon-chromium R-2R resistor ladder network divides the

reference current and provides the circuit with excellent

temperature tracking characteristics (0.05% of Full Scale

Range maximum linearity error over temperature). The cir-

cuit uses CMOS current switches and control logic to

achieve low power consumption and low output leakage

current errors. Special circuitry provides TTL logic input volt-

age level compatibility.

Double buffering allows these DACs to output a voltage

corresponding to one digital word while holding the next

digital word. This permits the simultaneous updating of any

number of DACs.

The DAC0830 series are the 8-bit members of a family of

microprocessor-compatible DACs (MICRO-DAC

™

Features

n Double-buffered, single-buffered or flow-through digital

data inputs

n Easy interchange and pin-compatible with 12-bit

DAC1230 series

n Direct interface to all popular microprocessors

n Linearity specified with zero and full scale adjust

only—NOT BEST STRAIGHT LINE FIT.

n Works with

10V reference-full 4-quadrant multiplication

n Can be used in the voltage switching mode

n Logic inputs which meet TTL voltage level specs (1.4V

logic threshold)

n Operates “STAND ALONE” (without µP) if desired

n Available in 20-pin small-outline or molded chip carrier

package

Key Specifications

n Current settling time: 1 µs

n Resolution: 8 bits

n Linearity: 8, 9, or 10 bits (guaranteed over temp.)

n Gain Tempco: 0.0002% FS/˚C

n Low power dissipation: 20 mW

n Single power supply: 5 to 15 V

Typical Application

00560801

BI-FET

™

and MICRO-DAC

™

are trademarks of National Semiconductor Corporation.

Z80

is a registered trademark of Zilog Corporation.

March 2002

DAC0830/DAC0832 8-Bit µP Compatible, Double-Buffered D to A Converters

Connection Diagrams (Top Views)

Dual-In-Line and

Small-Outline Packages

00560821

Molded Chip Carrier Package

00560822

DAC0830/DAC0832

www.national.com 2

Absolute Maximum Ratings (Notes 1,

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

)17V

Voltage at Any Digital Input V

to GND

Voltage at V

REF

Input

25V

Storage Temperature Range −65˚C to +150˚C

Package Dissipation

at T

=25˚C (Note 3) 500 mW

DC Voltage Applied to

OUT1

or I

OUT2

(Note 4) −100 mV to V

ESD Susceptability (Note 4) 800V

Lead Temperature (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260˚C

Dual-In-Line Package (ceramic) 300˚C

Surface Mount Package

Vapor Phase (60 sec.) 215˚C

Infrared (15 sec.) 220˚C

Operating Conditions

Temperature Range T

MIN

≤T

MAX

Part numbers with “LCN” suffix 0˚C to +70˚C

Part numbers with “LCWM” suffix 0˚C to +70˚C

Part numbers with “LCV” suffix 0˚C to +70˚C

Part numbers with “LCJ” suffix −40˚C to +85˚C

Part numbers with “LJ” suffix −55˚C to +125˚C

Voltage at Any Digital Input V

to GND

Electrical Characteristics

REF

=10.000 V

unless otherwise noted. Boldface limits apply over temperature, T

MIN

≤T

MAX

. For all other limits

=25˚C.

Parameter Conditions

See

Note

= 4.75 V

= 15.75 V

=5V

=12V

to 15 V

Limit

Units

Typ

(Note 12)

Tested

Limit

(Note 5)

Design

Limit

(Note 6)

CONVERTER CHARACTERISTICS

Resolution 8 8 8 bits

Linearity Error Max Zero and full scale adjusted 4, 8

−10V≤V

REF

≤+10V

DAC0830LJ & LCJ 0.05 0.05 % FSR

DAC0832LJ & LCJ 0.2 0.2 % FSR

DAC0830LCN, LCWM &

LCV

0.05 0.05 % FSR

DAC0831LCN 0.1 0.1 % FSR

DAC0832LCN, LCWM &

LCV

0.2 0.2 % FSR

Differential Nonlinearity Zero and full scale adjusted 4, 8

Max −10V≤V

REF

≤+10V

DAC0830LJ & LCJ 0.1 0.1 % FSR

DAC0832LJ & LCJ 0.4 0.4 % FSR

DAC0830LCN, LCWM &

LCV

0.1 0.1 % FSR

DAC0831LCN 0.2 0.2 % FSR

DAC0832LCN, LCWM &

LCV

0.4 0.4 % FSR

Monotonicity −10V≤V

REF

LJ & LCJ 4 88bits

≤+10V LCN, LCWM &

LCV

8 8 bits

Gain Error Max Using Internal R

0.2

1 %FS

−10V≤V

REF

≤+10V

Gain Error Tempco Max Using internal R

0.0002 0.0006 %

DAC0830/DAC0832

www.national.com3

Electrical Characteristics (Continued)

REF

=10.000 V

unless otherwise noted. Boldface limits apply over temperature, T

MIN

≤T

MAX

. For all other limits

=25˚C.

Parameter Conditions

See

Note

= 4.75 V

= 15.75 V

=5V

=12V

to 15 V

Limit

Units

Typ

(Note 12)

Tested

Limit

(Note 5)

Design

Limit

(Note 6)

CONVERTER CHARACTERISTICS

FS/˚C

Power Supply Rejection All digital inputs latched high

=14.5V to 15.5V 0.0002 0.0025 %

11.5V to 12.5V 0.0006 FSR/V

4.5V to 5.5V 0.013 0.015

Reference Max 15 20 20 kΩ

Input Min 15 10 10 kΩ

Output Feedthrough

Error

REF

=20 Vp-p, f=100 kHz

All data inputs latched low

3 mVp-p

Output

Leakage

Current Max

OUT1

All data inputs LJ & LCJ 10 100 100 nA

latched low LCN, LCWM &

LCV

50 100

OUT2

All data inputs LJ & LCJ 100 100 nA

latched high LCN, LCWM &

LCV

50 100

Output I

OUT1

All data inputs 45 pF

Capacitance I

OUT2

latched low 115

OUT1

All data inputs 130 pF

OUT2

latched

high

DIGITAL AND DC CHARACTERISTICS

Digital Input Max Logic Low LJ: 4.75V 0.6

Voltages LJ: 15.75V 0.8

LCJ: 4.75V 0.7 V

LCJ: 15.75V 0.8

LCN, LCWM, LCV 0.95 0.8

Min Logic High LJ & LCJ 2.0 2.0 V

LCN, LCWM, LCV 1.9 2.0

Digital Input Max Digital inputs

0.8V

Currents LJ & LCJ −50 −200 −200 µA

LCN, LCWM, LCV −160 −200 µA

Digital inputs

2.0V

LJ & LCJ 0.1 +10 +10 µA

LCN, LCWM, LCV +8 +10

Supply Current Max LJ & LCJ 1.2 3.5 3.5 mA

Drain LCN, LCWM, LCV 1.7 2.0

DAC0830/DAC0832

www.national.com 4

Electrical Characteristics

REF

=10.000 V

unless otherwise noted. Boldface limits apply over temperature, T

MIN

≤T

MAX

. For all other limits

=25˚C.

Symbol Parameter Conditions

See

Note

=15.75 V

=12

5% to 15

=4.75 V

Limit

Units

Typ

(Note 12)

Tested

Limit

(Note 5)

Design Limit

(Note 6)

Typ

(Note 12)

Tested

Limit

(Note 5)

Design

Limit

(Note 6)

AC CHARACTERISTICS

Current Setting V

=0V,

=5V

1.0 1.0 µs

Time

Write and XFER V

=0V,

=5V

11 100 250 375 600

Pulse Width Min 9 320 320 900 900

Data Setup Time V

=0V,

=5V

100 250 375 600

Min 320 320 900 900

Data Hold Time V

=0V,

=5V

30 50

Min 30 50

Control Setup

Time

=0V,

=5V

110 250 600 900

Min 320 320 1100 1100

Control Hold Time V

=0V,

=5V

10 0

Min 00

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

JMAX

, θ

, and the ambient temperature, T

. The maximum

allowable power dissipation at any temperature is P

=(T

JMAX

−T

)/θ

or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,

JMAX

= 125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N

package, this number increases to 100˚C/W and for the V package this number is 120˚C/W.

Note 4: For current switching applications, both I

OUT1

and I

OUT2

must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded

by approximately V

÷V

REF

. For example, if V

REF

=10Vthena1mVoffset, V

,onI

OUT1

or I

OUT2

will introduce an additional 0.01% linearity error.

Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.

Note 7: Guaranteed at V

REF

10 V

and V

REF

Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a

particular V

REF

value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees

that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xV

REF

of a

straight line which passes through zero and full scale.