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STM32F10xxx FSMC peripheral to drive external memories.pdf
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STM32F10xxx FSMC peripheral to drive external memories.pdf
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April 2009 Doc ID 14779 Rev 3 1/30
AN2784
Application note
Using the high-density STM32F10xxx FSMC
peripheral to drive external memories
Introduction
This application note describes how to use the High-density STM32F10xxx FSMC (flexible
static memory controller) peripheral to drive a set of external memories. To that aim, it gives
an overview of the STM32F10xxx FSMC controller. Then it provides memory interfacing
examples that include the typical FSMC configuration, the timing computation method and
the hardware connection.
This application note is based on memories mounted on the STM3210E-EVAL, which is the
evaluation board for High-density STM32F10xxx devices. The used memories are a 16-bit
asynchronous NOR Flash memory, an 8-bit NAND Flash memory and a 16-bit
asynchronous SRAM.
The STM32F10xxx firmware library, the different memory drivers and examples of use for
each of the memory types used in this application note, are available for download from the
STMicroelectronics website: www.st.com/mcu.
www.st.com
Contents AN2784
2/30 Doc ID 14779 Rev 3
Contents
1 Overview of the STM32F10xxx flexible static memory controller . . . . 5
2 Interfacing with a nonmultiplexed, asynchronous
16-bit NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 FSMC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Typical use of the FSMC to interface with a NOR Flash memory . . . . . 10
2.2 Timing computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Code execution from an external NOR Flash memory . . . . . . . . . . . . . . . 14
3 Interfacing with a nonmultiplexed, asynchronous 16-bit SRAM . . . . . 15
3.1 FSMC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 Typical use of the FSMC to interface with an SRAM . . . . . . . . . . . . . . . 16
3.2 Timing computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Using the external SRAM as a data memory . . . . . . . . . . . . . . . . . . . . . . 18
4 Interfacing with an 8-bit NAND Flash memory . . . . . . . . . . . . . . . . . . . 19
4.1 FSMC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.1 Typical use of the FSMC to interface with a NAND memory . . . . . . . . . 21
4.2 Timing computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Error correction code computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4.1 Error correction code (ECC) computation overview . . . . . . . . . . . . . . . . 25
4.4.2 Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5 STM32F10xxx FSMC configuration in 100-pin packages . . . . . . . . . . 27
5.1 Interfacing the FSMC with a NAND Flash memory . . . . . . . . . . . . . . . . . 27
5.2 Interfacing the FSMC with a NOR Flash memory . . . . . . . . . . . . . . . . . . 28
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AN2784 List of tables
Doc ID 14779 Rev 3 3/30
List of tables
Table 1. NOR Flash memory timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. STM32F10xxx parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. M29W128FL signal to FSMC pin correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. SRAM timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. IS61WV51216BLL signal to FSMC pin correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. NAND Flash memory timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. NAND512W3A signal to FSMC pin correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. NAND Flash memory connection to the FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. NOR Flash memory connection to the FSMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
List of figures AN2784
4/30 Doc ID 14779 Rev 3
List of figures
Figure 1. FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Asynchronous NOR Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Asynchronous NOR Flash write access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. 16-bit NOR Flash: M29W128FL/GL connection to STM32F10xxx . . . . . . . . . . . . . . . . . . . 13
Figure 6. SRAM asynchronous read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. SRAM asynchronous write access timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. 16-bit SRAM: IS61WV51216BLL connection to STM32F10xxx . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. FSMC NAND bank sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. NAND memory access timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. 8-bit NAND Flash: NAND512W3A2C/NAND512W3A2B connection to
STM32F10xxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Error detection flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AN2784 Overview of the STM32F10xxx flexible static memory controller
Doc ID 14779 Rev 3 5/30
1 Overview of the STM32F10xxx flexible static memory
controller
The flexible static memory controller (FSMC) is an external memory controller embedded in
High-density STM32F10xxx devices. Using it, the STM32F10xxx microcontroller can
interface with a variety of memories, including SRAM, NOR Flash and NAND Flash
memories.
The FSMC contains two types of controller:
● a NOR Flash/SRAM controller to interface with NOR Flash memories, SRAMs and
PSRAMs
● a NAND Flash/PC Card controller to interface with NAND Flash, PC Card, CF and CF+
memories
The controllers generate the appropriate signal timings to drive all these memories:
● 16 data lines to interface with 8-bit or 16-bit memory width
● 26 address lines to interface with up to 64 Mbytes memory size
● 5 independent memory Chip Select pins
● A set of control signals adapted for every type of memory:
– to control read/ write operations
– to actively communicate with memories which provide the Ready/Busy
signals and
the interrupt signals
– to interface with the PC Card in all possible configurations: PC card memory, PC
card I/O, true IDE
Figure 1 illustrates the FSMC block diagram.
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